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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Xilinx Zynq MPSoC Firmware layer4 *5 * Copyright (C) 2014-2018 Xilinx, Inc.6 *7 */8 9#ifndef _DT_BINDINGS_CLK_ZYNQMP_H10#define _DT_BINDINGS_CLK_ZYNQMP_H11 12#define IOPLL 013#define RPLL 114#define APLL 215#define DPLL 316#define VPLL 417#define IOPLL_TO_FPD 518#define RPLL_TO_FPD 619#define APLL_TO_LPD 720#define DPLL_TO_LPD 821#define VPLL_TO_LPD 922#define ACPU 1023#define ACPU_HALF 1124#define DBF_FPD 1225#define DBF_LPD 1326#define DBG_TRACE 1427#define DBG_TSTMP 1528#define DP_VIDEO_REF 1629#define DP_AUDIO_REF 1730#define DP_STC_REF 1831#define GDMA_REF 1932#define DPDMA_REF 2033#define DDR_REF 2134#define SATA_REF 2235#define PCIE_REF 2336#define GPU_REF 2437#define GPU_PP0_REF 2538#define GPU_PP1_REF 2639#define TOPSW_MAIN 2740#define TOPSW_LSBUS 2841#define GTGREF0_REF 2942#define LPD_SWITCH 3043#define LPD_LSBUS 3144#define USB0_BUS_REF 3245#define USB1_BUS_REF 3346#define USB3_DUAL_REF 3447#define USB0 3548#define USB1 3649#define CPU_R5 3750#define CPU_R5_CORE 3851#define CSU_SPB 3952#define CSU_PLL 4053#define PCAP 4154#define IOU_SWITCH 4255#define GEM_TSU_REF 4356#define GEM_TSU 4457#define GEM0_TX 4558#define GEM1_TX 4659#define GEM2_TX 4760#define GEM3_TX 4861#define GEM0_RX 4962#define GEM1_RX 5063#define GEM2_RX 5164#define GEM3_RX 5265#define QSPI_REF 5366#define SDIO0_REF 5467#define SDIO1_REF 5568#define UART0_REF 5669#define UART1_REF 5770#define SPI0_REF 5871#define SPI1_REF 5972#define NAND_REF 6073#define I2C0_REF 6174#define I2C1_REF 6275#define CAN0_REF 6376#define CAN1_REF 6477#define CAN0 6578#define CAN1 6679#define DLL_REF 6780#define ADMA_REF 6881#define TIMESTAMP_REF 6982#define AMS_REF 7083#define PL0_REF 7184#define PL1_REF 7285#define PL2_REF 7386#define PL3_REF 7487#define WDT 7588#define IOPLL_INT 7689#define IOPLL_PRE_SRC 7790#define IOPLL_HALF 7891#define IOPLL_INT_MUX 7992#define IOPLL_POST_SRC 8093#define RPLL_INT 8194#define RPLL_PRE_SRC 8295#define RPLL_HALF 8396#define RPLL_INT_MUX 8497#define RPLL_POST_SRC 8598#define APLL_INT 8699#define APLL_PRE_SRC 87100#define APLL_HALF 88101#define APLL_INT_MUX 89102#define APLL_POST_SRC 90103#define DPLL_INT 91104#define DPLL_PRE_SRC 92105#define DPLL_HALF 93106#define DPLL_INT_MUX 94107#define DPLL_POST_SRC 95108#define VPLL_INT 96109#define VPLL_PRE_SRC 97110#define VPLL_HALF 98111#define VPLL_INT_MUX 99112#define VPLL_POST_SRC 100113#define CAN0_MIO 101114#define CAN1_MIO 102115#define ACPU_FULL 103116#define GEM0_REF 104117#define GEM1_REF 105118#define GEM2_REF 106119#define GEM3_REF 107120#define GEM0_REF_UNG 108121#define GEM1_REF_UNG 109122#define GEM2_REF_UNG 110123#define GEM3_REF_UNG 111124#define LPD_WDT 112125 126#endif127