45 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * This header provides macros for JZ4775 DMA bindings.4 *5 * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>6 */7 8#ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__9#define __DT_BINDINGS_DMA_JZ4775_DMA_H__10 11/*12 * Request type numbers for the JZ4775 DMA controller (written to the DRTn13 * register for the channel).14 */15#define JZ4775_DMA_I2S0_TX 0x616#define JZ4775_DMA_I2S0_RX 0x717#define JZ4775_DMA_AUTO 0x818#define JZ4775_DMA_SADC_RX 0x919#define JZ4775_DMA_UART3_TX 0x0e20#define JZ4775_DMA_UART3_RX 0x0f21#define JZ4775_DMA_UART2_TX 0x1022#define JZ4775_DMA_UART2_RX 0x1123#define JZ4775_DMA_UART1_TX 0x1224#define JZ4775_DMA_UART1_RX 0x1325#define JZ4775_DMA_UART0_TX 0x1426#define JZ4775_DMA_UART0_RX 0x1527#define JZ4775_DMA_SSI0_TX 0x1628#define JZ4775_DMA_SSI0_RX 0x1729#define JZ4775_DMA_MSC0_TX 0x1a30#define JZ4775_DMA_MSC0_RX 0x1b31#define JZ4775_DMA_MSC1_TX 0x1c32#define JZ4775_DMA_MSC1_RX 0x1d33#define JZ4775_DMA_MSC2_TX 0x1e34#define JZ4775_DMA_MSC2_RX 0x1f35#define JZ4775_DMA_PCM0_TX 0x2036#define JZ4775_DMA_PCM0_RX 0x2137#define JZ4775_DMA_SMB0_TX 0x2438#define JZ4775_DMA_SMB0_RX 0x2539#define JZ4775_DMA_SMB1_TX 0x2640#define JZ4775_DMA_SMB1_RX 0x2741#define JZ4775_DMA_SMB2_TX 0x2842#define JZ4775_DMA_SMB2_RX 0x2943 44#endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */45