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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (C) 2022 MediaTek Inc.4 * Author: Yongqiang Niu <yongqiang.niu@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_GCE_MT8186_H8#define _DT_BINDINGS_GCE_MT8186_H9 10/* assign timeout 0 also means default */11#define CMDQ_NO_TIMEOUT 0xffffffff12#define CMDQ_TIMEOUT_DEFAULT 100013 14/* GCE thread priority */15#define CMDQ_THR_PRIO_LOWEST 016#define CMDQ_THR_PRIO_1 117#define CMDQ_THR_PRIO_2 218#define CMDQ_THR_PRIO_3 319#define CMDQ_THR_PRIO_4 420#define CMDQ_THR_PRIO_5 521#define CMDQ_THR_PRIO_6 622#define CMDQ_THR_PRIO_HIGHEST 723 24/* CPR count in 32bit register */25#define GCE_CPR_COUNT 131226 27/* GCE subsys table */28#define SUBSYS_1300XXXX 029#define SUBSYS_1400XXXX 130#define SUBSYS_1401XXXX 231#define SUBSYS_1402XXXX 332#define SUBSYS_1502XXXX 433#define SUBSYS_1582XXXX 534#define SUBSYS_1B00XXXX 635#define SUBSYS_1C00XXXX 736#define SUBSYS_1C10XXXX 837#define SUBSYS_1000XXXX 938#define SUBSYS_1001XXXX 1039#define SUBSYS_1020XXXX 1140#define SUBSYS_1021XXXX 1241#define SUBSYS_1022XXXX 1342#define SUBSYS_1023XXXX 1443#define SUBSYS_1060XXXX 1544#define SUBSYS_1602XXXX 1645#define SUBSYS_1608XXXX 1746#define SUBSYS_1700XXXX 1847#define SUBSYS_1701XXXX 1948#define SUBSYS_1702XXXX 2049#define SUBSYS_1703XXXX 2150#define SUBSYS_1706XXXX 2251#define SUBSYS_1A00XXXX 2352#define SUBSYS_1A01XXXX 2453#define SUBSYS_1A02XXXX 2554#define SUBSYS_1A03XXXX 2655#define SUBSYS_1A04XXXX 2756#define SUBSYS_1A05XXXX 2857#define SUBSYS_1A06XXXX 2958#define SUBSYS_NO_SUPPORT 9959 60/* GCE General Purpose Register (GPR) support61 * Leave note for scenario usage here62 */63/* GCE: write mask */64#define GCE_GPR_R00 0x0065#define GCE_GPR_R01 0x0166/* MDP: P1: JPEG dest */67#define GCE_GPR_R02 0x0268#define GCE_GPR_R03 0x0369/* MDP: PQ color */70#define GCE_GPR_R04 0x0471/* MDP: 2D sharpness */72#define GCE_GPR_R05 0x0573/* DISP: poll esd */74#define GCE_GPR_R06 0x0675#define GCE_GPR_R07 0x0776/* MDP: P4: 2D sharpness dst */77#define GCE_GPR_R08 0x0878#define GCE_GPR_R09 0x0979/* VCU: poll with timeout for GPR timer */80#define GCE_GPR_R10 0x0A81#define GCE_GPR_R11 0x0B82/* CMDQ: debug */83#define GCE_GPR_R12 0x0C84#define GCE_GPR_R13 0x0D85/* CMDQ: P7: debug */86#define GCE_GPR_R14 0x0E87#define GCE_GPR_R15 0x0F88 89/* GCE hardware events */90/* VDEC */91#define CMDQ_EVENT_LINE_COUNT_THRESHOLD_INTERRUPT 092#define CMDQ_EVENT_VDEC_INT 193#define CMDQ_EVENT_VDEC_PAUSE 294#define CMDQ_EVENT_VDEC_DEC_ERROR 395#define CMDQ_EVENT_MDEC_TIMEOUT 496#define CMDQ_EVENT_DRAM_ACCESS_DONE 597#define CMDQ_EVENT_INI_FETCH_RDY 698#define CMDQ_EVENT_PROCESS_FLAG 799#define CMDQ_EVENT_SEARCH_START_CODE_DONE 8100#define CMDQ_EVENT_REF_REORDER_DONE 9101#define CMDQ_EVENT_WP_TBLE_DONE 10102#define CMDQ_EVENT_COUNT_SRAM_CLR_DONE 11103#define CMDQ_EVENT_GCE_CNT_OP_THRESHOLD 15104#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_0 16105#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_1 17106#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_2 18107#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_3 19108#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_4 20109#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_5 21110#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_6 22111#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_7 23112#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_8 24113#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_9 25114#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_10 26115#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_11 27116#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_12 28117#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_13 29118#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_14 30119#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_15 31120#define CMDQ_EVENT_WPE_GCE_FRAME_DONE 32121 122/* CAM */123#define CMDQ_EVENT_ISP_FRAME_DONE_A 65124#define CMDQ_EVENT_ISP_FRAME_DONE_B 66125#define CMDQ_EVENT_CAMSV1_PASS1_DONE 70126#define CMDQ_EVENT_CAMSV2_PASS1_DONE 71127#define CMDQ_EVENT_CAMSV3_PASS1_DONE 72128#define CMDQ_EVENT_MRAW_0_PASS1_DONE 73129#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 75130#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 76131#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 77132#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 78133#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 79134#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 80135#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 81136#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 82137#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 83138#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 84139#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 85140#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 86141#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 87142#define CMDQ_EVENT_TG_OVRUN_A_INT 88143#define CMDQ_EVENT_DMA_R1_ERROR_A_INT 89144#define CMDQ_EVENT_TG_OVRUN_B_INT 90145#define CMDQ_EVENT_DMA_R1_ERROR_B_INT 91146#define CMDQ_EVENT_TG_OVRUN_M0_INT 94147#define CMDQ_EVENT_R1_ERROR_M0_INT 95148#define CMDQ_EVENT_TG_GRABERR_M0_INT 96149#define CMDQ_EVENT_TG_GRABERR_A_INT 98150#define CMDQ_EVENT_CQ_VR_SNAP_A_INT 99151#define CMDQ_EVENT_TG_GRABERR_B_INT 100152#define CMDQ_EVENT_CQ_VR_SNAP_B_INT 101153/* VENC */154#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 129155#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 130156#define CMDQ_EVENT_JPGENC_CMDQ_DONE 131157#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 132158#define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE 133159#define CMDQ_EVENT_VENC_CMDQ_PPS_DONE 136160#define CMDQ_EVENT_VENC_CMDQ_SPS_DONE 137161#define CMDQ_EVENT_VENC_CMDQ_VPS_DONE 138162/* IPE */163#define CMDQ_EVENT_FDVT_DONE 161164#define CMDQ_EVENT_FE_DONE 162165#define CMDQ_EVENT_RSC_DONE 163166#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 164167#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 165168/* IMG2 */169#define CMDQ_EVENT_GCE_IMG2_EVENT0 193170#define CMDQ_EVENT_GCE_IMG2_EVENT1 194171#define CMDQ_EVENT_GCE_IMG2_EVENT2 195172#define CMDQ_EVENT_GCE_IMG2_EVENT3 196173#define CMDQ_EVENT_GCE_IMG2_EVENT4 197174#define CMDQ_EVENT_GCE_IMG2_EVENT5 198175#define CMDQ_EVENT_GCE_IMG2_EVENT6 199176#define CMDQ_EVENT_GCE_IMG2_EVENT7 200177#define CMDQ_EVENT_GCE_IMG2_EVENT8 201178#define CMDQ_EVENT_GCE_IMG2_EVENT9 202179#define CMDQ_EVENT_GCE_IMG2_EVENT10 203180#define CMDQ_EVENT_GCE_IMG2_EVENT11 204181#define CMDQ_EVENT_GCE_IMG2_EVENT12 205182#define CMDQ_EVENT_GCE_IMG2_EVENT13 206183#define CMDQ_EVENT_GCE_IMG2_EVENT14 207184#define CMDQ_EVENT_GCE_IMG2_EVENT15 208185#define CMDQ_EVENT_GCE_IMG2_EVENT16 209186#define CMDQ_EVENT_GCE_IMG2_EVENT17 210187#define CMDQ_EVENT_GCE_IMG2_EVENT18 211188#define CMDQ_EVENT_GCE_IMG2_EVENT19 212189#define CMDQ_EVENT_GCE_IMG2_EVENT20 213190#define CMDQ_EVENT_GCE_IMG2_EVENT21 214191#define CMDQ_EVENT_GCE_IMG2_EVENT22 215192#define CMDQ_EVENT_GCE_IMG2_EVENT23 216193/* IMG1 */194#define CMDQ_EVENT_GCE_IMG1_EVENT0 225195#define CMDQ_EVENT_GCE_IMG1_EVENT1 226196#define CMDQ_EVENT_GCE_IMG1_EVENT2 227197#define CMDQ_EVENT_GCE_IMG1_EVENT3 228198#define CMDQ_EVENT_GCE_IMG1_EVENT4 229199#define CMDQ_EVENT_GCE_IMG1_EVENT5 230200#define CMDQ_EVENT_GCE_IMG1_EVENT6 231201#define CMDQ_EVENT_GCE_IMG1_EVENT7 232202#define CMDQ_EVENT_GCE_IMG1_EVENT8 233203#define CMDQ_EVENT_GCE_IMG1_EVENT9 234204#define CMDQ_EVENT_GCE_IMG1_EVENT10 235205#define CMDQ_EVENT_GCE_IMG1_EVENT11 236206#define CMDQ_EVENT_GCE_IMG1_EVENT12 237207#define CMDQ_EVENT_GCE_IMG1_EVENT13 238208#define CMDQ_EVENT_GCE_IMG1_EVENT14 239209#define CMDQ_EVENT_GCE_IMG1_EVENT15 240210#define CMDQ_EVENT_GCE_IMG1_EVENT16 241211#define CMDQ_EVENT_GCE_IMG1_EVENT17 242212#define CMDQ_EVENT_GCE_IMG1_EVENT18 243213#define CMDQ_EVENT_GCE_IMG1_EVENT19 244214#define CMDQ_EVENT_GCE_IMG1_EVENT20 245215#define CMDQ_EVENT_GCE_IMG1_EVENT21 246216#define CMDQ_EVENT_GCE_IMG1_EVENT22 247217#define CMDQ_EVENT_GCE_IMG1_EVENT23 248218/* MDP */219#define CMDQ_EVENT_MDP_RDMA0_SOF 256220#define CMDQ_EVENT_MDP_RDMA1_SOF 257221#define CMDQ_EVENT_MDP_AAL0_SOF 258222#define CMDQ_EVENT_MDP_AAL1_SOF 259223#define CMDQ_EVENT_MDP_HDR0_SOF 260224#define CMDQ_EVENT_MDP_RSZ0_SOF 261225#define CMDQ_EVENT_MDP_RSZ1_SOF 262226#define CMDQ_EVENT_MDP_WROT0_SOF 263227#define CMDQ_EVENT_MDP_WROT1_SOF 264228#define CMDQ_EVENT_MDP_TDSHP0_SOF 265229#define CMDQ_EVENT_MDP_TDSHP1_SOF 266230#define CMDQ_EVENT_IMG_DL_RELAY0_SOF 267231#define CMDQ_EVENT_IMG_DL_RELAY1_SOF 268232#define CMDQ_EVENT_MDP_COLOR0_SOF 269233#define CMDQ_EVENT_MDP_WROT3_FRAME_DONE 288234#define CMDQ_EVENT_MDP_WROT2_FRAME_DONE 289235#define CMDQ_EVENT_MDP_WROT1_FRAME_DONE 290236#define CMDQ_EVENT_MDP_WROT0_FRAME_DONE 291237#define CMDQ_EVENT_MDP_TDSHP3_FRAME_DONE 292238#define CMDQ_EVENT_MDP_TDSHP2_FRAME_DONE 293239#define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE 294240#define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE 295241#define CMDQ_EVENT_MDP_RSZ3_FRAME_DONE 296242#define CMDQ_EVENT_MDP_RSZ2_FRAME_DONE 297243#define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE 298244#define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE 299245#define CMDQ_EVENT_MDP_RDMA3_FRAME_DONE 300246#define CMDQ_EVENT_MDP_RDMA2_FRAME_DONE 301247#define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE 302248#define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE 303249#define CMDQ_EVENT_MDP_HDR1_FRAME_DONE 304250#define CMDQ_EVENT_MDP_HDR0_FRAME_DONE 305251#define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE 306252#define CMDQ_EVENT_MDP_AAL3_FRAME_DONE 307253#define CMDQ_EVENT_MDP_AAL2_FRAME_DONE 308254#define CMDQ_EVENT_MDP_AAL1_FRAME_DONE 309255#define CMDQ_EVENT_MDP_AAL0_FRAME_DONE 310256#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 320257#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 321258#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 322259#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 323260#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 324261#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 325262#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 326263#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 327264#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 328265#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329266#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 330267#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 331268#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 332269#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 333270#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 334271#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 335272#define CMDQ_EVENT_MDP_WROT3_SW_RST_DONE_ENG_EVENT 336273#define CMDQ_EVENT_MDP_WROT2_SW_RST_DONE_ENG_EVENT 337274#define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT 338275#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT 339276#define CMDQ_EVENT_MDP_RDMA3_SW_RST_DONE_ENG_EVENT 340277#define CMDQ_EVENT_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 341278#define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 342279#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 343280/* DISP */281#define CMDQ_EVENT_DISP_OVL0_SOF 384282#define CMDQ_EVENT_DISP_OVL0_2L_SOF 385283#define CMDQ_EVENT_DISP_RDMA0_SOF 386284#define CMDQ_EVENT_DISP_RSZ0_SOF 387285#define CMDQ_EVENT_DISP_COLOR0_SOF 388286#define CMDQ_EVENT_DISP_CCORR0_SOF 389287#define CMDQ_EVENT_DISP_CCORR1_SOF 390288#define CMDQ_EVENT_DISP_AAL0_SOF 391289#define CMDQ_EVENT_DISP_GAMMA0_SOF 392290#define CMDQ_EVENT_DISP_POSTMASK0_SOF 393291#define CMDQ_EVENT_DISP_DITHER0_SOF 394292#define CMDQ_EVENT_DISP_CM0_SOF 395293#define CMDQ_EVENT_DISP_SPR0_SOF 396294#define CMDQ_EVENT_DISP_DSC_WRAP0_SOF 397295#define CMDQ_EVENT_DSI0_SOF 398296#define CMDQ_EVENT_DISP_WDMA0_SOF 399297#define CMDQ_EVENT_DISP_PWM0_SOF 400298#define CMDQ_EVENT_DSI0_FRAME_DONE 410299#define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE 411300#define CMDQ_EVENT_DISP_SPR0_FRAME_DONE 412301#define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE 413302#define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE 414303#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 415304#define CMDQ_EVENT_DISP_OVL0_FRAME_DONE 416305#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE 417306#define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE 418307#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE 420308#define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE 421309#define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE 422310#define CMDQ_EVENT_DISP_CM0_FRAME_DONE 423311#define CMDQ_EVENT_DISP_CCORR1_FRAME_DONE 424312#define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE 425313#define CMDQ_EVENT_DISP_AAL0_FRAME_DONE 426314#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0 434315#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1 435316#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2 436317#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3 437318#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4 438319#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5 439320#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6 440321#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7 441322#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8 442323#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9 443324#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10 444325#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11 445326#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12 446327#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13 447328#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14 448329#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15 449330#define CMDQ_EVENT_DSI0_TE_ENG_EVENT 450331#define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT 451332#define CMDQ_EVENT_DSI0_DONE_ENG_EVENT 452333#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 453334#define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT 454335#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT 455336#define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT 456337#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT 457338#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0 458339#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1 459340#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2 460341#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3 461342#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4 462343#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5 463344#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6 464345#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7 465346#define CMDQ_EVENT_OUT_EVENT_0 898347 348/* CMDQ sw tokens349 * Following definitions are gce sw token which may use by clients350 * event operation API.351 * Note that token 512 to 639 may set secure352 */353 354/* end of hw event and begin of sw token */355#define CMDQ_MAX_HW_EVENT 512356 357/* Config thread notify trigger thread */358#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640359/* Trigger thread notify config thread */360#define CMDQ_SYNC_TOKEN_STREAM_EOF 641361/* Block Trigger thread until the ESD check finishes. */362#define CMDQ_SYNC_TOKEN_ESD_EOF 642363#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643364/* check CABC setup finish */365#define CMDQ_SYNC_TOKEN_CABC_EOF 644366 367/* Notify normal CMDQ there are some secure task done368 * MUST NOT CHANGE, this token sync with secure world369 */370#define CMDQ_SYNC_SECURE_THR_EOF 647371 372/* CMDQ use sw token */373#define CMDQ_SYNC_TOKEN_USER_0 649374#define CMDQ_SYNC_TOKEN_USER_1 650375#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651376#define CMDQ_SYNC_TOKEN_TPR_LOCK 652377 378/* ISP sw token */379#define CMDQ_SYNC_TOKEN_MSS 665380#define CMDQ_SYNC_TOKEN_MSF 666381 382/* DISP sw token */383#define CMDQ_SYNC_TOKEN_SODI 671384 385/* GPR access tokens (for register backup)386 * There are 15 32-bit GPR, 3 GPR form a set387 * (64-bit for address, 32-bit for value)388 * MUST NOT CHANGE, these tokens sync with MDP389 */390#define CMDQ_SYNC_TOKEN_GPR_SET_0 700391#define CMDQ_SYNC_TOKEN_GPR_SET_1 701392#define CMDQ_SYNC_TOKEN_GPR_SET_2 702393#define CMDQ_SYNC_TOKEN_GPR_SET_3 703394#define CMDQ_SYNC_TOKEN_GPR_SET_4 704395 396/* Resource lock event to control resource in GCE thread */397#define CMDQ_SYNC_RESOURCE_WROT0 710398#define CMDQ_SYNC_RESOURCE_WROT1 711399 400/* event for gpr timer, used in sleep and poll with timeout */401#define CMDQ_TOKEN_GPR_TIMER_R0 994402#define CMDQ_TOKEN_GPR_TIMER_R1 995403#define CMDQ_TOKEN_GPR_TIMER_R2 996404#define CMDQ_TOKEN_GPR_TIMER_R3 997405#define CMDQ_TOKEN_GPR_TIMER_R4 998406#define CMDQ_TOKEN_GPR_TIMER_R5 999407#define CMDQ_TOKEN_GPR_TIMER_R6 1000408#define CMDQ_TOKEN_GPR_TIMER_R7 1001409#define CMDQ_TOKEN_GPR_TIMER_R8 1002410#define CMDQ_TOKEN_GPR_TIMER_R9 1003411#define CMDQ_TOKEN_GPR_TIMER_R10 1004412#define CMDQ_TOKEN_GPR_TIMER_R11 1005413#define CMDQ_TOKEN_GPR_TIMER_R12 1006414#define CMDQ_TOKEN_GPR_TIMER_R13 1007415#define CMDQ_TOKEN_GPR_TIMER_R14 1008416#define CMDQ_TOKEN_GPR_TIMER_R15 1009417 418#define CMDQ_EVENT_MAX 0x3FF419/* CMDQ sw tokens END */420 421#endif422