304 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H7#define _DT_BINDINGS_QCOM_SPMI_VADC_H8 9/* Voltage ADC channels */10#define VADC_USBIN 0x0011#define VADC_DCIN 0x0112#define VADC_VCHG_SNS 0x0213#define VADC_SPARE1_03 0x0314#define VADC_USB_ID_MV 0x0415#define VADC_VCOIN 0x0516#define VADC_VBAT_SNS 0x0617#define VADC_VSYS 0x0718#define VADC_DIE_TEMP 0x0819#define VADC_REF_625MV 0x0920#define VADC_REF_1250MV 0x0a21#define VADC_CHG_TEMP 0x0b22#define VADC_SPARE1 0x0c23#define VADC_SPARE2 0x0d24#define VADC_GND_REF 0x0e25#define VADC_VDD_VADC 0x0f26 27#define VADC_P_MUX1_1_1 0x1028#define VADC_P_MUX2_1_1 0x1129#define VADC_P_MUX3_1_1 0x1230#define VADC_P_MUX4_1_1 0x1331#define VADC_P_MUX5_1_1 0x1432#define VADC_P_MUX6_1_1 0x1533#define VADC_P_MUX7_1_1 0x1634#define VADC_P_MUX8_1_1 0x1735#define VADC_P_MUX9_1_1 0x1836#define VADC_P_MUX10_1_1 0x1937#define VADC_P_MUX11_1_1 0x1a38#define VADC_P_MUX12_1_1 0x1b39#define VADC_P_MUX13_1_1 0x1c40#define VADC_P_MUX14_1_1 0x1d41#define VADC_P_MUX15_1_1 0x1e42#define VADC_P_MUX16_1_1 0x1f43 44#define VADC_P_MUX1_1_3 0x2045#define VADC_P_MUX2_1_3 0x2146#define VADC_P_MUX3_1_3 0x2247#define VADC_P_MUX4_1_3 0x2348#define VADC_P_MUX5_1_3 0x2449#define VADC_P_MUX6_1_3 0x2550#define VADC_P_MUX7_1_3 0x2651#define VADC_P_MUX8_1_3 0x2752#define VADC_P_MUX9_1_3 0x2853#define VADC_P_MUX10_1_3 0x2954#define VADC_P_MUX11_1_3 0x2a55#define VADC_P_MUX12_1_3 0x2b56#define VADC_P_MUX13_1_3 0x2c57#define VADC_P_MUX14_1_3 0x2d58#define VADC_P_MUX15_1_3 0x2e59#define VADC_P_MUX16_1_3 0x2f60 61#define VADC_LR_MUX1_BAT_THERM 0x3062#define VADC_LR_MUX2_BAT_ID 0x3163#define VADC_LR_MUX3_XO_THERM 0x3264#define VADC_LR_MUX4_AMUX_THM1 0x3365#define VADC_LR_MUX5_AMUX_THM2 0x3466#define VADC_LR_MUX6_AMUX_THM3 0x3567#define VADC_LR_MUX7_HW_ID 0x3668#define VADC_LR_MUX8_AMUX_THM4 0x3769#define VADC_LR_MUX9_AMUX_THM5 0x3870#define VADC_LR_MUX10_USB_ID 0x3971#define VADC_AMUX_PU1 0x3a72#define VADC_AMUX_PU2 0x3b73#define VADC_LR_MUX3_BUF_XO_THERM 0x3c74 75#define VADC_LR_MUX1_PU1_BAT_THERM 0x7076#define VADC_LR_MUX2_PU1_BAT_ID 0x7177#define VADC_LR_MUX3_PU1_XO_THERM 0x7278#define VADC_LR_MUX4_PU1_AMUX_THM1 0x7379#define VADC_LR_MUX5_PU1_AMUX_THM2 0x7480#define VADC_LR_MUX6_PU1_AMUX_THM3 0x7581#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x7682#define VADC_LR_MUX8_PU1_AMUX_THM4 0x7783#define VADC_LR_MUX9_PU1_AMUX_THM5 0x7884#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x7985#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c86 87#define VADC_LR_MUX1_PU2_BAT_THERM 0xb088#define VADC_LR_MUX2_PU2_BAT_ID 0xb189#define VADC_LR_MUX3_PU2_XO_THERM 0xb290#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb391#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb492#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb593#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb694#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb795#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb896#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb997#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc98 99#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0100#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1101#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2102#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3103#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4104#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5105#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6106#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7107#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8108#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9109#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc110 111/* ADC channels for SPMI PMIC5 */112 113#define ADC5_REF_GND 0x00114#define ADC5_1P25VREF 0x01115#define ADC5_VREF_VADC 0x02116#define ADC5_VREF_VADC5_DIV_3 0x82117#define ADC5_VPH_PWR 0x83118#define ADC5_VBAT_SNS 0x84119#define ADC5_VCOIN 0x85120#define ADC5_DIE_TEMP 0x06121#define ADC5_USB_IN_I 0x07122#define ADC5_USB_IN_V_16 0x08123#define ADC5_CHG_TEMP 0x09124#define ADC5_BAT_THERM 0x0a125#define ADC5_BAT_ID 0x0b126#define ADC5_XO_THERM 0x0c127#define ADC5_AMUX_THM1 0x0d128#define ADC5_AMUX_THM2 0x0e129#define ADC5_AMUX_THM3 0x0f130#define ADC5_AMUX_THM4 0x10131#define ADC5_AMUX_THM5 0x11132#define ADC5_GPIO1 0x12133#define ADC5_GPIO2 0x13134#define ADC5_GPIO3 0x14135#define ADC5_GPIO4 0x15136#define ADC5_GPIO5 0x16137#define ADC5_GPIO6 0x17138#define ADC5_GPIO7 0x18139#define ADC5_SBUx 0x99140#define ADC5_MID_CHG_DIV6 0x1e141#define ADC5_OFF 0xff142 143/* 30k pull-up1 */144#define ADC5_BAT_THERM_30K_PU 0x2a145#define ADC5_BAT_ID_30K_PU 0x2b146#define ADC5_XO_THERM_30K_PU 0x2c147#define ADC5_AMUX_THM1_30K_PU 0x2d148#define ADC5_AMUX_THM2_30K_PU 0x2e149#define ADC5_AMUX_THM3_30K_PU 0x2f150#define ADC5_AMUX_THM4_30K_PU 0x30151#define ADC5_AMUX_THM5_30K_PU 0x31152#define ADC5_GPIO1_30K_PU 0x32153#define ADC5_GPIO2_30K_PU 0x33154#define ADC5_GPIO3_30K_PU 0x34155#define ADC5_GPIO4_30K_PU 0x35156#define ADC5_GPIO5_30K_PU 0x36157#define ADC5_GPIO6_30K_PU 0x37158#define ADC5_GPIO7_30K_PU 0x38159#define ADC5_SBUx_30K_PU 0x39160 161/* 100k pull-up2 */162#define ADC5_BAT_THERM_100K_PU 0x4a163#define ADC5_BAT_ID_100K_PU 0x4b164#define ADC5_XO_THERM_100K_PU 0x4c165#define ADC5_AMUX_THM1_100K_PU 0x4d166#define ADC5_AMUX_THM2_100K_PU 0x4e167#define ADC5_AMUX_THM3_100K_PU 0x4f168#define ADC5_AMUX_THM4_100K_PU 0x50169#define ADC5_AMUX_THM5_100K_PU 0x51170#define ADC5_GPIO1_100K_PU 0x52171#define ADC5_GPIO2_100K_PU 0x53172#define ADC5_GPIO3_100K_PU 0x54173#define ADC5_GPIO4_100K_PU 0x55174#define ADC5_GPIO5_100K_PU 0x56175#define ADC5_GPIO6_100K_PU 0x57176#define ADC5_GPIO7_100K_PU 0x58177#define ADC5_SBUx_100K_PU 0x59178 179/* 400k pull-up3 */180#define ADC5_BAT_THERM_400K_PU 0x6a181#define ADC5_BAT_ID_400K_PU 0x6b182#define ADC5_XO_THERM_400K_PU 0x6c183#define ADC5_AMUX_THM1_400K_PU 0x6d184#define ADC5_AMUX_THM2_400K_PU 0x6e185#define ADC5_AMUX_THM3_400K_PU 0x6f186#define ADC5_AMUX_THM4_400K_PU 0x70187#define ADC5_AMUX_THM5_400K_PU 0x71188#define ADC5_GPIO1_400K_PU 0x72189#define ADC5_GPIO2_400K_PU 0x73190#define ADC5_GPIO3_400K_PU 0x74191#define ADC5_GPIO4_400K_PU 0x75192#define ADC5_GPIO5_400K_PU 0x76193#define ADC5_GPIO6_400K_PU 0x77194#define ADC5_GPIO7_400K_PU 0x78195#define ADC5_SBUx_400K_PU 0x79196 197/* 1/3 Divider */198#define ADC5_GPIO1_DIV3 0x92199#define ADC5_GPIO2_DIV3 0x93200#define ADC5_GPIO3_DIV3 0x94201#define ADC5_GPIO4_DIV3 0x95202#define ADC5_GPIO5_DIV3 0x96203#define ADC5_GPIO6_DIV3 0x97204#define ADC5_GPIO7_DIV3 0x98205#define ADC5_SBUx_DIV3 0x99206 207/* Current and combined current/voltage channels */208#define ADC5_INT_EXT_ISENSE 0xa1209#define ADC5_PARALLEL_ISENSE 0xa5210#define ADC5_CUR_REPLICA_VDS 0xa7211#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9212#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab213#define ADC5_EXT_SENS_OFFSET 0xad214 215#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0216#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1217#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2218#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3219#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4220#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5221 222#define ADC5_MAX_CHANNEL 0xc0223 224/* ADC channels for ADC for PMIC7 */225 226#define ADC7_REF_GND 0x00227#define ADC7_1P25VREF 0x01228#define ADC7_VREF_VADC 0x02229#define ADC7_DIE_TEMP 0x03230 231#define ADC7_AMUX_THM1 0x04232#define ADC7_AMUX_THM2 0x05233#define ADC7_AMUX_THM3 0x06234#define ADC7_AMUX_THM4 0x07235#define ADC7_AMUX_THM5 0x08236#define ADC7_AMUX_THM6 0x09237#define ADC7_GPIO1 0x0a238#define ADC7_GPIO2 0x0b239#define ADC7_GPIO3 0x0c240#define ADC7_GPIO4 0x0d241 242#define ADC7_SMB_TEMP 0x06243#define ADC7_CHG_TEMP 0x10244#define ADC7_USB_IN_V_16 0x11245#define ADC7_VDC_16 0x12246#define ADC7_CC1_ID 0x13247#define ADC7_VREF_BAT_THERM 0x15248#define ADC7_IIN_FB 0x17249#define ADC7_ICHG_SMB 0x18250#define ADC7_IIN_SMB 0x19251 252/* 30k pull-up1 */253#define ADC7_AMUX_THM1_30K_PU 0x24254#define ADC7_AMUX_THM2_30K_PU 0x25255#define ADC7_AMUX_THM3_30K_PU 0x26256#define ADC7_AMUX_THM4_30K_PU 0x27257#define ADC7_AMUX_THM5_30K_PU 0x28258#define ADC7_AMUX_THM6_30K_PU 0x29259#define ADC7_GPIO1_30K_PU 0x2a260#define ADC7_GPIO2_30K_PU 0x2b261#define ADC7_GPIO3_30K_PU 0x2c262#define ADC7_GPIO4_30K_PU 0x2d263#define ADC7_CC1_ID_30K_PU 0x33264 265/* 100k pull-up2 */266#define ADC7_AMUX_THM1_100K_PU 0x44267#define ADC7_AMUX_THM2_100K_PU 0x45268#define ADC7_AMUX_THM3_100K_PU 0x46269#define ADC7_AMUX_THM4_100K_PU 0x47270#define ADC7_AMUX_THM5_100K_PU 0x48271#define ADC7_AMUX_THM6_100K_PU 0x49272#define ADC7_GPIO1_100K_PU 0x4a273#define ADC7_GPIO2_100K_PU 0x4b274#define ADC7_GPIO3_100K_PU 0x4c275#define ADC7_GPIO4_100K_PU 0x4d276#define ADC7_CC1_ID_100K_PU 0x53277 278/* 400k pull-up3 */279#define ADC7_AMUX_THM1_400K_PU 0x64280#define ADC7_AMUX_THM2_400K_PU 0x65281#define ADC7_AMUX_THM3_400K_PU 0x66282#define ADC7_AMUX_THM4_400K_PU 0x67283#define ADC7_AMUX_THM5_400K_PU 0x68284#define ADC7_AMUX_THM6_400K_PU 0x69285#define ADC7_GPIO1_400K_PU 0x6a286#define ADC7_GPIO2_400K_PU 0x6b287#define ADC7_GPIO3_400K_PU 0x6c288#define ADC7_GPIO4_400K_PU 0x6d289#define ADC7_CC1_ID_400K_PU 0x73290 291/* 1/3 Divider */292#define ADC7_GPIO1_DIV3 0x8a293#define ADC7_GPIO2_DIV3 0x8b294#define ADC7_GPIO3_DIV3 0x8c295#define ADC7_GPIO4_DIV3 0x8d296 297#define ADC7_VPH_PWR 0x8e298#define ADC7_VBAT_SNS 0x8f299 300#define ADC7_SBUx 0x94301#define ADC7_VBAT_2S_MID 0x96302 303#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */304