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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2022 Collabora Ltd.4 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>5 */6 7#ifndef _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_8#define _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_9 10#include <dt-bindings/memory/mtk-memory-port.h>11 12#define M4U_LARB0_ID 013#define M4U_LARB1_ID 114#define M4U_LARB2_ID 215#define M4U_LARB3_ID 316#define M4U_LARB4_ID 417 18/* larb0 */19#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)20#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)21#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 2)22#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)23#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4)24#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 5)25#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB0_ID, 6)26#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 7)27#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 8)28#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 9)29#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 10)30#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 11)31#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 12)32#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 13)33 34/* larb1 */35#define M4U_PORT_VDEC_MC MTK_M4U_ID(M4U_LARB1_ID, 0)36#define M4U_PORT_VDEC_PP MTK_M4U_ID(M4U_LARB1_ID, 1)37#define M4U_PORT_VDEC_UFO MTK_M4U_ID(M4U_LARB1_ID, 2)38#define M4U_PORT_VDEC_VLD MTK_M4U_ID(M4U_LARB1_ID, 3)39#define M4U_PORT_VDEC_VLD2 MTK_M4U_ID(M4U_LARB1_ID, 4)40#define M4U_PORT_VDEC_AVC_MV MTK_M4U_ID(M4U_LARB1_ID, 5)41#define M4U_PORT_VDEC_PRED_RD MTK_M4U_ID(M4U_LARB1_ID, 6)42#define M4U_PORT_VDEC_PRED_WR MTK_M4U_ID(M4U_LARB1_ID, 7)43#define M4U_PORT_VDEC_PPWRAP MTK_M4U_ID(M4U_LARB1_ID, 8)44 45/* larb2 */46#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0)47#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1)48#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2)49#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3)50#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4)51#define M4U_PORT_CAM_IMGO_S MTK_M4U_ID(M4U_LARB2_ID, 5)52#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6)53#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7)54#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8)55#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9)56#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10)57#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11)58#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12)59#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13)60#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14)61#define M4U_PORT_CAM_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15)62#define M4U_PORT_CAM_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16)63#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17)64#define M4U_PORT_CAM_RB MTK_M4U_ID(M4U_LARB2_ID, 18)65#define M4U_PORT_CAM_RP MTK_M4U_ID(M4U_LARB2_ID, 19)66#define M4U_PORT_CAM_WR MTK_M4U_ID(M4U_LARB2_ID, 20)67 68/* larb3 */69#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0)70#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1)71#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2)72#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3)73#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4)74#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 5)75#define M4U_PORT_REMDC_SDMA MTK_M4U_ID(M4U_LARB3_ID, 6)76#define M4U_PORT_REMDC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 7)77#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8)78#define M4U_PORT_JPGENC_SDMA MTK_M4U_ID(M4U_LARB3_ID, 9)79#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 10)80#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 11)81#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 12)82#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 13)83#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 14)84#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 15)85#define M4U_PORT_REMDC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 16)86#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 17)87#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 18)88 89/* larb4 */90#define M4U_PORT_MJC_MV_RD MTK_M4U_ID(M4U_LARB4_ID, 0)91#define M4U_PORT_MJC_MV_WR MTK_M4U_ID(M4U_LARB4_ID, 1)92#define M4U_PORT_MJC_DMA_RD MTK_M4U_ID(M4U_LARB4_ID, 2)93#define M4U_PORT_MJC_DMA_WR MTK_M4U_ID(M4U_LARB4_ID, 3)94 95#endif96