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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2018 MediaTek Inc.4 * Author: Yong Wu <yong.wu@mediatek.com>5 */6#ifndef _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_7#define _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_8 9#include <dt-bindings/memory/mtk-memory-port.h>10 11#define M4U_LARB0_ID 012#define M4U_LARB1_ID 113#define M4U_LARB2_ID 214#define M4U_LARB3_ID 315#define M4U_LARB4_ID 416#define M4U_LARB5_ID 517#define M4U_LARB6_ID 618#define M4U_LARB7_ID 719 20/* larb0 */21#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)22#define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1)23#define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2)24#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)25#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)26#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)27#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)28#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)29#define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8)30#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9)31 32/* larb1 */33#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)34#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)35#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)36#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)37#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)38#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)39#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)40 41/* larb2 VPU0 */42#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0)43#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1)44#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2)45 46/* larb3 VPU1 */47#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0)48#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1)49#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2)50#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3)51#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4)52 53/* larb4 */54#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0)55#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1)56#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2)57#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3)58#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4)59#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5)60#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6)61#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7)62#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8)63#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9)64#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10)65 66/* larb5 */67#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0)68#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1)69#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2)70#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3)71#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4)72#define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5)73#define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6)74#define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7)75#define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8)76#define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9)77#define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10)78#define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11)79#define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12)80#define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13)81#define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14)82#define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15)83#define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16)84#define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17)85#define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18)86#define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19)87#define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20)88#define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21)89#define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22)90#define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23)91#define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24)92 93/* larb6 */94#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0)95#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1)96#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2)97#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3)98#define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4)99#define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5)100#define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6)101#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7)102#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8)103#define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9)104#define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10)105#define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11)106#define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12)107#define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13)108#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14)109#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15)110#define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16)111#define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17)112#define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18)113#define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19)114#define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20)115#define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21)116#define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22)117#define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23)118#define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24)119#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25)120#define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26)121#define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27)122#define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28)123#define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29)124#define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30)125 126/* CCU */127#define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0)128#define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1)129 130#endif131