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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Yong Wu <yong.wu@mediatek.com>5 */6#ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_7#define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_8 9#include <dt-bindings/memory/mtk-memory-port.h>10 11/*12 * MM IOMMU supports 16GB dma address. We separate it to four ranges:13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters14 * locate in anyone region. BUT:15 * a) Make sure all the ports inside a larb are in one range.16 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.17 *18 * This is the suggested mapping in this SoC:19 *20 * modules dma-address-region larbs-ports21 * disp 0 ~ 4G larb0/1/2/322 * vcodec 4G ~ 8G larb19/20/21/22/23/2423 * cam/mdp 8G ~ 12G the other larbs.24 * N/A 12G ~ 16G25 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/126 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/327 *28 * This SoC have two IOMMU HWs, this is the detailed connected information:29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/2830 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/2731 */32 33/* MM IOMMU ports */34/* larb0 */35#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0)36#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1)37#define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(0, 2)38#define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3)39#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4)40#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5)41 42/* larb1 */43#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0)44#define M4U_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 1)45#define M4U_PORT_L1_DISP_OVL0_RDMA0 MTK_M4U_ID(1, 2)46#define M4U_PORT_L1_DISP_OVL0_RDMA1 MTK_M4U_ID(1, 3)47#define M4U_PORT_L1_DISP_OVL0_HDR MTK_M4U_ID(1, 4)48#define M4U_PORT_L1_DISP_FAKE0 MTK_M4U_ID(1, 5)49 50/* larb2 */51#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0)52#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(2, 1)53#define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(2, 2)54#define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(2, 3)55#define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(2, 4)56 57/* larb3 */58#define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0)59#define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(3, 1)60#define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(3, 2)61#define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(3, 3)62#define M4U_PORT_L3_HDR_DS MTK_M4U_ID(3, 4)63#define M4U_PORT_L3_HDR_ADL MTK_M4U_ID(3, 5)64#define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(3, 6)65 66/* larb4 */67#define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(4, 0)68#define M4U_PORT_L4_MDP_FG MTK_M4U_ID(4, 1)69#define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(4, 2)70#define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(4, 3)71#define M4U_PORT_L4_FAKE MTK_M4U_ID(4, 4)72 73/* larb5 */74#define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0)75#define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(5, 1)76#define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(5, 2)77#define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(5, 3)78#define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(5, 4)79#define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(5, 5)80#define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(5, 6)81#define M4U_PORT_L5_FAKE MTK_M4U_ID(5, 7)82 83/* larb6 */84#define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(6, 0)85#define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(6, 1)86#define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(6, 2)87#define M4U_PORT_L6_FAKE MTK_M4U_ID(6, 3)88 89/* larb7 */90#define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0)91#define M4U_PORT_L7_IMG_WPE_RDMA1 MTK_M4U_ID(7, 1)92#define M4U_PORT_L7_IMG_WPE_WDMA0 MTK_M4U_ID(7, 2)93 94/* larb8 */95#define M4U_PORT_L8_IMG_WPE_RDMA0 MTK_M4U_ID(8, 0)96#define M4U_PORT_L8_IMG_WPE_RDMA1 MTK_M4U_ID(8, 1)97#define M4U_PORT_L8_IMG_WPE_WDMA0 MTK_M4U_ID(8, 2)98 99/* larb9 */100#define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0)101#define M4U_PORT_L9_IMG_IMGBI_T1_A MTK_M4U_ID(9, 1)102#define M4U_PORT_L9_IMG_IMGCI_T1_A MTK_M4U_ID(9, 2)103#define M4U_PORT_L9_IMG_SMTI_T1_A MTK_M4U_ID(9, 3)104#define M4U_PORT_L9_IMG_TNCSTI_T1_A MTK_M4U_ID(9, 4)105#define M4U_PORT_L9_IMG_TNCSTI_T4_A MTK_M4U_ID(9, 5)106#define M4U_PORT_L9_IMG_YUVO_T1_A MTK_M4U_ID(9, 6)107#define M4U_PORT_L9_IMG_TIMGO_T1_A MTK_M4U_ID(9, 7)108#define M4U_PORT_L9_IMG_YUVO_T2_A MTK_M4U_ID(9, 8)109#define M4U_PORT_L9_IMG_IMGI_T1_B MTK_M4U_ID(9, 9)110#define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10)111#define M4U_PORT_L9_IMG_IMGCI_T1_B MTK_M4U_ID(9, 11)112#define M4U_PORT_L9_IMG_YUVO_T5_A MTK_M4U_ID(9, 12)113#define M4U_PORT_L9_IMG_SMTI_T1_B MTK_M4U_ID(9, 13)114#define M4U_PORT_L9_IMG_TNCSO_T1_A MTK_M4U_ID(9, 14)115#define M4U_PORT_L9_IMG_SMTO_T1_A MTK_M4U_ID(9, 15)116#define M4U_PORT_L9_IMG_TNCSTO_T1_A MTK_M4U_ID(9, 16)117#define M4U_PORT_L9_IMG_YUVO_T2_B MTK_M4U_ID(9, 17)118#define M4U_PORT_L9_IMG_YUVO_T5_B MTK_M4U_ID(9, 18)119#define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19)120 121/* larb10 */122#define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0)123#define M4U_PORT_L10_IMG_IMGCI_D1_A MTK_M4U_ID(10, 1)124#define M4U_PORT_L10_IMG_DEPI_D1_A MTK_M4U_ID(10, 2)125#define M4U_PORT_L10_IMG_DMGI_D1_A MTK_M4U_ID(10, 3)126#define M4U_PORT_L10_IMG_VIPI_D1_A MTK_M4U_ID(10, 4)127#define M4U_PORT_L10_IMG_TNRWI_D1_A MTK_M4U_ID(10, 5)128#define M4U_PORT_L10_IMG_RECI_D1_A MTK_M4U_ID(10, 6)129#define M4U_PORT_L10_IMG_SMTI_D1_A MTK_M4U_ID(10, 7)130#define M4U_PORT_L10_IMG_SMTI_D6_A MTK_M4U_ID(10, 8)131#define M4U_PORT_L10_IMG_PIMGI_P1_A MTK_M4U_ID(10, 9)132#define M4U_PORT_L10_IMG_PIMGBI_P1_A MTK_M4U_ID(10, 10)133#define M4U_PORT_L10_IMG_PIMGCI_P1_A MTK_M4U_ID(10, 11)134#define M4U_PORT_L10_IMG_PIMGI_P1_B MTK_M4U_ID(10, 12)135#define M4U_PORT_L10_IMG_PIMGBI_P1_B MTK_M4U_ID(10, 13)136#define M4U_PORT_L10_IMG_PIMGCI_P1_B MTK_M4U_ID(10, 14)137#define M4U_PORT_L10_IMG_IMG3O_D1_A MTK_M4U_ID(10, 15)138#define M4U_PORT_L10_IMG_IMG4O_D1_A MTK_M4U_ID(10, 16)139#define M4U_PORT_L10_IMG_IMG3CO_D1_A MTK_M4U_ID(10, 17)140#define M4U_PORT_L10_IMG_FEO_D1_A MTK_M4U_ID(10, 18)141#define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19)142#define M4U_PORT_L10_IMG_TNRWO_D1_A MTK_M4U_ID(10, 20)143#define M4U_PORT_L10_IMG_SMTO_D1_A MTK_M4U_ID(10, 21)144#define M4U_PORT_L10_IMG_WROT_P1_A MTK_M4U_ID(10, 22)145#define M4U_PORT_L10_IMG_WROT_P1_B MTK_M4U_ID(10, 23)146 147/* larb11 */148#define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0)149#define M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A MTK_M4U_ID(11, 1)150#define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A MTK_M4U_ID(11, 2)151#define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A MTK_M4U_ID(11, 3)152#define M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A MTK_M4U_ID(11, 4)153#define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A MTK_M4U_ID(11, 5)154#define M4U_PORT_L11_IMG_WPE_EIS_CQ0_A MTK_M4U_ID(11, 6)155#define M4U_PORT_L11_IMG_WPE_EIS_CQ1_A MTK_M4U_ID(11, 7)156#define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A MTK_M4U_ID(11, 8)157#define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A MTK_M4U_ID(11, 9)158 159/* larb12 */160#define M4U_PORT_L12_IMG_FDVT_RDA MTK_M4U_ID(12, 0)161#define M4U_PORT_L12_IMG_FDVT_RDB MTK_M4U_ID(12, 1)162#define M4U_PORT_L12_IMG_FDVT_WRA MTK_M4U_ID(12, 2)163#define M4U_PORT_L12_IMG_FDVT_WRB MTK_M4U_ID(12, 3)164#define M4U_PORT_L12_IMG_ME_RDMA MTK_M4U_ID(12, 4)165#define M4U_PORT_L12_IMG_ME_WDMA MTK_M4U_ID(12, 5)166#define M4U_PORT_L12_IMG_DVS_RDMA MTK_M4U_ID(12, 6)167#define M4U_PORT_L12_IMG_DVS_WDMA MTK_M4U_ID(12, 7)168#define M4U_PORT_L12_IMG_DVP_RDMA MTK_M4U_ID(12, 8)169#define M4U_PORT_L12_IMG_DVP_WDMA MTK_M4U_ID(12, 9)170 171/* larb13 */172#define M4U_PORT_L13_CAM_CAMSV_CQI_E1 MTK_M4U_ID(13, 0)173#define M4U_PORT_L13_CAM_CAMSV_CQI_E2 MTK_M4U_ID(13, 1)174#define M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0 MTK_M4U_ID(13, 2)175#define M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0 MTK_M4U_ID(13, 3)176#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(13, 4)177#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(13, 5)178#define M4U_PORT_L13_CAM_GCAMSV_A_UFEO_0 MTK_M4U_ID(13, 6)179#define M4U_PORT_L13_CAM_GCAMSV_B_UFEO_0 MTK_M4U_ID(13, 7)180#define M4U_PORT_L13_CAM_PDAI_0 MTK_M4U_ID(13, 8)181#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 9)182 183/* larb14 */184#define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1 MTK_M4U_ID(14, 0)185#define M4U_PORT_L14_CAM_SCAMSV_A_IMGO_1 MTK_M4U_ID(14, 1)186#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(14, 2)187#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(14, 3)188#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_0 MTK_M4U_ID(14, 4)189#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1 MTK_M4U_ID(14, 5)190#define M4U_PORT_L14_CAM_IPUI MTK_M4U_ID(14, 6)191#define M4U_PORT_L14_CAM_IPU2I MTK_M4U_ID(14, 7)192#define M4U_PORT_L14_CAM_IPUO MTK_M4U_ID(14, 8)193#define M4U_PORT_L14_CAM_IPU2O MTK_M4U_ID(14, 9)194#define M4U_PORT_L14_CAM_IPU3O MTK_M4U_ID(14, 10)195#define M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1 MTK_M4U_ID(14, 11)196#define M4U_PORT_L14_CAM_GCAMSV_B_UFEO_1 MTK_M4U_ID(14, 12)197#define M4U_PORT_L14_CAM_PDAI_1 MTK_M4U_ID(14, 13)198#define M4U_PORT_L14_CAM_PDAO MTK_M4U_ID(14, 14)199 200/* larb15: null */201 202/* larb16 */203#define M4U_PORT_L16_CAM_IMGO_R1 MTK_M4U_ID(16, 0)204#define M4U_PORT_L16_CAM_CQI_R1 MTK_M4U_ID(16, 1)205#define M4U_PORT_L16_CAM_CQI_R2 MTK_M4U_ID(16, 2)206#define M4U_PORT_L16_CAM_BPCI_R1 MTK_M4U_ID(16, 3)207#define M4U_PORT_L16_CAM_LSCI_R1 MTK_M4U_ID(16, 4)208#define M4U_PORT_L16_CAM_RAWI_R2 MTK_M4U_ID(16, 5)209#define M4U_PORT_L16_CAM_RAWI_R3 MTK_M4U_ID(16, 6)210#define M4U_PORT_L16_CAM_UFDI_R2 MTK_M4U_ID(16, 7)211#define M4U_PORT_L16_CAM_UFDI_R3 MTK_M4U_ID(16, 8)212#define M4U_PORT_L16_CAM_RAWI_R4 MTK_M4U_ID(16, 9)213#define M4U_PORT_L16_CAM_RAWI_R5 MTK_M4U_ID(16, 10)214#define M4U_PORT_L16_CAM_AAI_R1 MTK_M4U_ID(16, 11)215#define M4U_PORT_L16_CAM_FHO_R1 MTK_M4U_ID(16, 12)216#define M4U_PORT_L16_CAM_AAO_R1 MTK_M4U_ID(16, 13)217#define M4U_PORT_L16_CAM_TSFSO_R1 MTK_M4U_ID(16, 14)218#define M4U_PORT_L16_CAM_FLKO_R1 MTK_M4U_ID(16, 15)219 220/* larb17 */221#define M4U_PORT_L17_CAM_YUVO_R1 MTK_M4U_ID(17, 0)222#define M4U_PORT_L17_CAM_YUVO_R3 MTK_M4U_ID(17, 1)223#define M4U_PORT_L17_CAM_YUVCO_R1 MTK_M4U_ID(17, 2)224#define M4U_PORT_L17_CAM_YUVO_R2 MTK_M4U_ID(17, 3)225#define M4U_PORT_L17_CAM_RZH1N2TO_R1 MTK_M4U_ID(17, 4)226#define M4U_PORT_L17_CAM_DRZS4NO_R1 MTK_M4U_ID(17, 5)227#define M4U_PORT_L17_CAM_TNCSO_R1 MTK_M4U_ID(17, 6)228 229/* larb18 */230#define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0)231#define M4U_PORT_L18_CAM_CCUO MTK_M4U_ID(18, 1)232#define M4U_PORT_L18_CAM_CCUI2 MTK_M4U_ID(18, 2)233#define M4U_PORT_L18_CAM_CCUO2 MTK_M4U_ID(18, 3)234 235/* larb19 */236#define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0)237#define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1)238#define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2)239#define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3)240#define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4)241#define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5)242#define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6)243#define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(19, 7)244#define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(19, 8)245#define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9)246#define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10)247#define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11)248#define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(19, 12)249#define M4U_PORT_L19_JPGDEC_WDMA0 MTK_M4U_ID(19, 13)250#define M4U_PORT_L19_JPGDEC_BSDMA0 MTK_M4U_ID(19, 14)251#define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(19, 15)252#define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(19, 16)253#define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(19, 17)254#define M4U_PORT_L19_JPGDEC_WDMA1 MTK_M4U_ID(19, 18)255#define M4U_PORT_L19_JPGDEC_BSDMA1 MTK_M4U_ID(19, 19)256#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(19, 20)257#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21)258#define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(19, 22)259#define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(19, 23)260#define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24)261#define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25)262#define M4U_PORT_L19_VENC_SUB_R_CHROMA MTK_M4U_ID(19, 26)263 264/* larb20 */265#define M4U_PORT_L20_VENC_RCPU MTK_M4U_ID(20, 0)266#define M4U_PORT_L20_VENC_REC MTK_M4U_ID(20, 1)267#define M4U_PORT_L20_VENC_BSDMA MTK_M4U_ID(20, 2)268#define M4U_PORT_L20_VENC_SV_COMV MTK_M4U_ID(20, 3)269#define M4U_PORT_L20_VENC_RD_COMV MTK_M4U_ID(20, 4)270#define M4U_PORT_L20_VENC_NBM_RDMA MTK_M4U_ID(20, 5)271#define M4U_PORT_L20_VENC_NBM_RDMA_LITE MTK_M4U_ID(20, 6)272#define M4U_PORT_L20_JPGENC_Y_RDMA MTK_M4U_ID(20, 7)273#define M4U_PORT_L20_JPGENC_C_RDMA MTK_M4U_ID(20, 8)274#define M4U_PORT_L20_JPGENC_Q_TABLE MTK_M4U_ID(20, 9)275#define M4U_PORT_L20_VENC_SUB_W_LUMA MTK_M4U_ID(20, 10)276#define M4U_PORT_L20_VENC_FCS_NBM_RDMA MTK_M4U_ID(20, 11)277#define M4U_PORT_L20_JPGENC_BSDMA MTK_M4U_ID(20, 12)278#define M4U_PORT_L20_JPGDEC_WDMA0 MTK_M4U_ID(20, 13)279#define M4U_PORT_L20_JPGDEC_BSDMA0 MTK_M4U_ID(20, 14)280#define M4U_PORT_L20_VENC_NBM_WDMA MTK_M4U_ID(20, 15)281#define M4U_PORT_L20_VENC_NBM_WDMA_LITE MTK_M4U_ID(20, 16)282#define M4U_PORT_L20_VENC_FCS_NBM_WDMA MTK_M4U_ID(20, 17)283#define M4U_PORT_L20_JPGDEC_WDMA1 MTK_M4U_ID(20, 18)284#define M4U_PORT_L20_JPGDEC_BSDMA1 MTK_M4U_ID(20, 19)285#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(20, 20)286#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(20, 21)287#define M4U_PORT_L20_VENC_CUR_LUMA MTK_M4U_ID(20, 22)288#define M4U_PORT_L20_VENC_CUR_CHROMA MTK_M4U_ID(20, 23)289#define M4U_PORT_L20_VENC_REF_LUMA MTK_M4U_ID(20, 24)290#define M4U_PORT_L20_VENC_REF_CHROMA MTK_M4U_ID(20, 25)291#define M4U_PORT_L20_VENC_SUB_R_CHROMA MTK_M4U_ID(20, 26)292 293/* larb21 */294#define M4U_PORT_L21_VDEC_MC_EXT MTK_M4U_ID(21, 0)295#define M4U_PORT_L21_VDEC_UFO_EXT MTK_M4U_ID(21, 1)296#define M4U_PORT_L21_VDEC_PP_EXT MTK_M4U_ID(21, 2)297#define M4U_PORT_L21_VDEC_PRED_RD_EXT MTK_M4U_ID(21, 3)298#define M4U_PORT_L21_VDEC_PRED_WR_EXT MTK_M4U_ID(21, 4)299#define M4U_PORT_L21_VDEC_PPWRAP_EXT MTK_M4U_ID(21, 5)300#define M4U_PORT_L21_VDEC_TILE_EXT MTK_M4U_ID(21, 6)301#define M4U_PORT_L21_VDEC_VLD_EXT MTK_M4U_ID(21, 7)302#define M4U_PORT_L21_VDEC_VLD2_EXT MTK_M4U_ID(21, 8)303#define M4U_PORT_L21_VDEC_AVC_MV_EXT MTK_M4U_ID(21, 9)304 305/* larb22 */306#define M4U_PORT_L22_VDEC_MC_EXT MTK_M4U_ID(22, 0)307#define M4U_PORT_L22_VDEC_UFO_EXT MTK_M4U_ID(22, 1)308#define M4U_PORT_L22_VDEC_PP_EXT MTK_M4U_ID(22, 2)309#define M4U_PORT_L22_VDEC_PRED_RD_EXT MTK_M4U_ID(22, 3)310#define M4U_PORT_L22_VDEC_PRED_WR_EXT MTK_M4U_ID(22, 4)311#define M4U_PORT_L22_VDEC_PPWRAP_EXT MTK_M4U_ID(22, 5)312#define M4U_PORT_L22_VDEC_TILE_EXT MTK_M4U_ID(22, 6)313#define M4U_PORT_L22_VDEC_VLD_EXT MTK_M4U_ID(22, 7)314#define M4U_PORT_L22_VDEC_VLD2_EXT MTK_M4U_ID(22, 8)315#define M4U_PORT_L22_VDEC_AVC_MV_EXT MTK_M4U_ID(22, 9)316 317/* larb23 */318#define M4U_PORT_L23_VDEC_UFO_ENC_EXT MTK_M4U_ID(23, 0)319#define M4U_PORT_L23_VDEC_RDMA_EXT MTK_M4U_ID(23, 1)320 321/* larb24 */322#define M4U_PORT_L24_VDEC_LAT0_VLD_EXT MTK_M4U_ID(24, 0)323#define M4U_PORT_L24_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(24, 1)324#define M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT MTK_M4U_ID(24, 2)325#define M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(24, 3)326#define M4U_PORT_L24_VDEC_LAT0_TILE_EXT MTK_M4U_ID(24, 4)327#define M4U_PORT_L24_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(24, 5)328#define M4U_PORT_L24_VDEC_LAT1_VLD_EXT MTK_M4U_ID(24, 6)329#define M4U_PORT_L24_VDEC_LAT1_VLD2_EXT MTK_M4U_ID(24, 7)330#define M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT MTK_M4U_ID(24, 8)331#define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT MTK_M4U_ID(24, 9)332#define M4U_PORT_L24_VDEC_LAT1_TILE_EXT MTK_M4U_ID(24, 10)333#define M4U_PORT_L24_VDEC_LAT1_WDMA_EXT MTK_M4U_ID(24, 11)334 335/* larb25 */336#define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0)337#define M4U_PORT_L25_CAM_MRAW0_CQI_M1 MTK_M4U_ID(25, 1)338#define M4U_PORT_L25_CAM_MRAW0_CQI_M2 MTK_M4U_ID(25, 2)339#define M4U_PORT_L25_CAM_MRAW0_IMGO_M1 MTK_M4U_ID(25, 3)340#define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1 MTK_M4U_ID(25, 4)341#define M4U_PORT_L25_CAM_MRAW2_LSCI_M1 MTK_M4U_ID(25, 5)342#define M4U_PORT_L25_CAM_MRAW2_CQI_M1 MTK_M4U_ID(25, 6)343#define M4U_PORT_L25_CAM_MRAW2_CQI_M2 MTK_M4U_ID(25, 7)344#define M4U_PORT_L25_CAM_MRAW2_IMGO_M1 MTK_M4U_ID(25, 8)345#define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1 MTK_M4U_ID(25, 9)346#define M4U_PORT_L25_CAM_MRAW0_AFO_M1 MTK_M4U_ID(25, 10)347#define M4U_PORT_L25_CAM_MRAW2_AFO_M1 MTK_M4U_ID(25, 11)348 349/* larb26 */350#define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_ID(26, 0)351#define M4U_PORT_L26_CAM_MRAW1_CQI_M1 MTK_M4U_ID(26, 1)352#define M4U_PORT_L26_CAM_MRAW1_CQI_M2 MTK_M4U_ID(26, 2)353#define M4U_PORT_L26_CAM_MRAW1_IMGO_M1 MTK_M4U_ID(26, 3)354#define M4U_PORT_L26_CAM_MRAW1_IMGBO_M1 MTK_M4U_ID(26, 4)355#define M4U_PORT_L26_CAM_MRAW3_LSCI_M1 MTK_M4U_ID(26, 5)356#define M4U_PORT_L26_CAM_MRAW3_CQI_M1 MTK_M4U_ID(26, 6)357#define M4U_PORT_L26_CAM_MRAW3_CQI_M2 MTK_M4U_ID(26, 7)358#define M4U_PORT_L26_CAM_MRAW3_IMGO_M1 MTK_M4U_ID(26, 8)359#define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1 MTK_M4U_ID(26, 9)360#define M4U_PORT_L26_CAM_MRAW1_AFO_M1 MTK_M4U_ID(26, 10)361#define M4U_PORT_L26_CAM_MRAW3_AFO_M1 MTK_M4U_ID(26, 11)362 363/* larb27 */364#define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0)365#define M4U_PORT_L27_CAM_CQI_R1 MTK_M4U_ID(27, 1)366#define M4U_PORT_L27_CAM_CQI_R2 MTK_M4U_ID(27, 2)367#define M4U_PORT_L27_CAM_BPCI_R1 MTK_M4U_ID(27, 3)368#define M4U_PORT_L27_CAM_LSCI_R1 MTK_M4U_ID(27, 4)369#define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5)370#define M4U_PORT_L27_CAM_RAWI_R3 MTK_M4U_ID(27, 6)371#define M4U_PORT_L27_CAM_UFDI_R2 MTK_M4U_ID(27, 7)372#define M4U_PORT_L27_CAM_UFDI_R3 MTK_M4U_ID(27, 8)373#define M4U_PORT_L27_CAM_RAWI_R4 MTK_M4U_ID(27, 9)374#define M4U_PORT_L27_CAM_RAWI_R5 MTK_M4U_ID(27, 10)375#define M4U_PORT_L27_CAM_AAI_R1 MTK_M4U_ID(27, 11)376#define M4U_PORT_L27_CAM_FHO_R1 MTK_M4U_ID(27, 12)377#define M4U_PORT_L27_CAM_AAO_R1 MTK_M4U_ID(27, 13)378#define M4U_PORT_L27_CAM_TSFSO_R1 MTK_M4U_ID(27, 14)379#define M4U_PORT_L27_CAM_FLKO_R1 MTK_M4U_ID(27, 15)380 381/* larb28 */382#define M4U_PORT_L28_CAM_YUVO_R1 MTK_M4U_ID(28, 0)383#define M4U_PORT_L28_CAM_YUVO_R3 MTK_M4U_ID(28, 1)384#define M4U_PORT_L28_CAM_YUVCO_R1 MTK_M4U_ID(28, 2)385#define M4U_PORT_L28_CAM_YUVO_R2 MTK_M4U_ID(28, 3)386#define M4U_PORT_L28_CAM_RZH1N2TO_R1 MTK_M4U_ID(28, 4)387#define M4U_PORT_L28_CAM_DRZS4NO_R1 MTK_M4U_ID(28, 5)388#define M4U_PORT_L28_CAM_TNCSO_R1 MTK_M4U_ID(28, 6)389 390/* Infra iommu ports */391/* PCIe1: read: BIT16; write BIT17. */392#define IOMMU_PORT_INFRA_PCIE1 MTK_IFAIOMMU_PERI_ID(16)393/* PCIe0: read: BIT18; write BIT19. */394#define IOMMU_PORT_INFRA_PCIE0 MTK_IFAIOMMU_PERI_ID(18)395#define IOMMU_PORT_INFRA_SSUSB_P3_R MTK_IFAIOMMU_PERI_ID(20)396#define IOMMU_PORT_INFRA_SSUSB_P3_W MTK_IFAIOMMU_PERI_ID(21)397#define IOMMU_PORT_INFRA_SSUSB_P2_R MTK_IFAIOMMU_PERI_ID(22)398#define IOMMU_PORT_INFRA_SSUSB_P2_W MTK_IFAIOMMU_PERI_ID(23)399#define IOMMU_PORT_INFRA_SSUSB_P1_1_R MTK_IFAIOMMU_PERI_ID(24)400#define IOMMU_PORT_INFRA_SSUSB_P1_1_W MTK_IFAIOMMU_PERI_ID(25)401#define IOMMU_PORT_INFRA_SSUSB_P1_0_R MTK_IFAIOMMU_PERI_ID(26)402#define IOMMU_PORT_INFRA_SSUSB_P1_0_W MTK_IFAIOMMU_PERI_ID(27)403#define IOMMU_PORT_INFRA_SSUSB2_R MTK_IFAIOMMU_PERI_ID(28)404#define IOMMU_PORT_INFRA_SSUSB2_W MTK_IFAIOMMU_PERI_ID(29)405#define IOMMU_PORT_INFRA_SSUSB_R MTK_IFAIOMMU_PERI_ID(30)406#define IOMMU_PORT_INFRA_SSUSB_W MTK_IFAIOMMU_PERI_ID(31)407 408#endif409