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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */3 4#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H5#define DT_BINDINGS_MEMORY_TEGRA234_MC_H6 7/* special clients */8#define TEGRA234_SID_INVALID 0x009#define TEGRA234_SID_PASSTHROUGH 0x7f10 11/* ISO stream IDs */12#define TEGRA234_SID_ISO_NVDISPLAY 0x0113#define TEGRA234_SID_ISO_VI 0x0214#define TEGRA234_SID_ISO_VIFALC 0x0315#define TEGRA234_SID_ISO_VI2 0x0416#define TEGRA234_SID_ISO_VI2FALC 0x0517#define TEGRA234_SID_ISO_VI_VM2 0x0618#define TEGRA234_SID_ISO_VI2_VM2 0x0719 20/* NISO0 stream IDs */21#define TEGRA234_SID_AON 0x0122#define TEGRA234_SID_APE 0x0223#define TEGRA234_SID_HDA 0x0324#define TEGRA234_SID_GPCDMA 0x0425#define TEGRA234_SID_ETR 0x0526#define TEGRA234_SID_MGBE 0x0627#define TEGRA234_SID_NVDISPLAY 0x0728#define TEGRA234_SID_DCE 0x0829#define TEGRA234_SID_PSC 0x0930#define TEGRA234_SID_RCE 0x0a31#define TEGRA234_SID_SCE 0x0b32#define TEGRA234_SID_UFSHC 0x0c33#define TEGRA234_SID_APE_1 0x0d34#define TEGRA234_SID_GPCDMA_1 0x0e35#define TEGRA234_SID_GPCDMA_2 0x0f36#define TEGRA234_SID_GPCDMA_3 0x1037#define TEGRA234_SID_GPCDMA_4 0x1138#define TEGRA234_SID_PCIE0 0x1239#define TEGRA234_SID_PCIE4 0x1340#define TEGRA234_SID_PCIE5 0x1441#define TEGRA234_SID_PCIE6 0x1542#define TEGRA234_SID_RCE_VM2 0x1643#define TEGRA234_SID_RCE_SERVER 0x1744#define TEGRA234_SID_SMMU_TEST 0x1845#define TEGRA234_SID_UFS_1 0x1946#define TEGRA234_SID_UFS_2 0x1a47#define TEGRA234_SID_UFS_3 0x1b48#define TEGRA234_SID_UFS_4 0x1c49#define TEGRA234_SID_UFS_5 0x1d50#define TEGRA234_SID_UFS_6 0x1e51#define TEGRA234_SID_PCIE9 0x1f52#define TEGRA234_SID_VSE_GPCDMA_VM0 0x2053#define TEGRA234_SID_VSE_GPCDMA_VM1 0x2154#define TEGRA234_SID_VSE_GPCDMA_VM2 0x2255#define TEGRA234_SID_NVDLA1 0x2356#define TEGRA234_SID_NVENC 0x2457#define TEGRA234_SID_NVJPG1 0x2558#define TEGRA234_SID_OFA 0x2659#define TEGRA234_SID_MGBE_VF1 0x4960#define TEGRA234_SID_MGBE_VF2 0x4a61#define TEGRA234_SID_MGBE_VF3 0x4b62#define TEGRA234_SID_MGBE_VF4 0x4c63#define TEGRA234_SID_MGBE_VF5 0x4d64#define TEGRA234_SID_MGBE_VF6 0x4e65#define TEGRA234_SID_MGBE_VF7 0x4f66#define TEGRA234_SID_MGBE_VF8 0x5067#define TEGRA234_SID_MGBE_VF9 0x5168#define TEGRA234_SID_MGBE_VF10 0x5269#define TEGRA234_SID_MGBE_VF11 0x5370#define TEGRA234_SID_MGBE_VF12 0x5471#define TEGRA234_SID_MGBE_VF13 0x5572#define TEGRA234_SID_MGBE_VF14 0x5673#define TEGRA234_SID_MGBE_VF15 0x5774#define TEGRA234_SID_MGBE_VF16 0x5875#define TEGRA234_SID_MGBE_VF17 0x5976#define TEGRA234_SID_MGBE_VF18 0x5a77#define TEGRA234_SID_MGBE_VF19 0x5b78#define TEGRA234_SID_MGBE_VF20 0x5c79#define TEGRA234_SID_APE_2 0x5e80#define TEGRA234_SID_APE_3 0x5f81#define TEGRA234_SID_UFS_7 0x6082#define TEGRA234_SID_UFS_8 0x6183#define TEGRA234_SID_UFS_9 0x6284#define TEGRA234_SID_UFS_10 0x6385#define TEGRA234_SID_UFS_11 0x6486#define TEGRA234_SID_UFS_12 0x6587#define TEGRA234_SID_UFS_13 0x6688#define TEGRA234_SID_UFS_14 0x6789#define TEGRA234_SID_UFS_15 0x6890#define TEGRA234_SID_UFS_16 0x6991#define TEGRA234_SID_UFS_17 0x6a92#define TEGRA234_SID_UFS_18 0x6b93#define TEGRA234_SID_UFS_19 0x6c94#define TEGRA234_SID_UFS_20 0x6d95#define TEGRA234_SID_GPCDMA_5 0x6e96#define TEGRA234_SID_GPCDMA_6 0x6f97#define TEGRA234_SID_GPCDMA_7 0x7098#define TEGRA234_SID_GPCDMA_8 0x7199#define TEGRA234_SID_GPCDMA_9 0x72100 101/* NISO1 stream IDs */102#define TEGRA234_SID_SDMMC1A 0x01103#define TEGRA234_SID_SDMMC4 0x02104#define TEGRA234_SID_EQOS 0x03105#define TEGRA234_SID_HWMP_PMA 0x04106#define TEGRA234_SID_PCIE1 0x05107#define TEGRA234_SID_PCIE2 0x06108#define TEGRA234_SID_PCIE3 0x07109#define TEGRA234_SID_PCIE7 0x08110#define TEGRA234_SID_PCIE8 0x09111#define TEGRA234_SID_PCIE10 0x0b112#define TEGRA234_SID_QSPI0 0x0c113#define TEGRA234_SID_QSPI1 0x0d114#define TEGRA234_SID_XUSB_HOST 0x0e115#define TEGRA234_SID_XUSB_DEV 0x0f116#define TEGRA234_SID_BPMP 0x10117#define TEGRA234_SID_FSI 0x11118#define TEGRA234_SID_PVA0_VM0 0x12119#define TEGRA234_SID_PVA0_VM1 0x13120#define TEGRA234_SID_PVA0_VM2 0x14121#define TEGRA234_SID_PVA0_VM3 0x15122#define TEGRA234_SID_PVA0_VM4 0x16123#define TEGRA234_SID_PVA0_VM5 0x17124#define TEGRA234_SID_PVA0_VM6 0x18125#define TEGRA234_SID_PVA0_VM7 0x19126#define TEGRA234_SID_XUSB_VF0 0x1a127#define TEGRA234_SID_XUSB_VF1 0x1b128#define TEGRA234_SID_XUSB_VF2 0x1c129#define TEGRA234_SID_XUSB_VF3 0x1d130#define TEGRA234_SID_EQOS_VF1 0x1e131#define TEGRA234_SID_EQOS_VF2 0x1f132#define TEGRA234_SID_EQOS_VF3 0x20133#define TEGRA234_SID_EQOS_VF4 0x21134#define TEGRA234_SID_ISP_VM2 0x22135#define TEGRA234_SID_HOST1X 0x27136#define TEGRA234_SID_ISP 0x28137#define TEGRA234_SID_NVDEC 0x29138#define TEGRA234_SID_NVJPG 0x2a139#define TEGRA234_SID_NVDLA0 0x2b140#define TEGRA234_SID_PVA0 0x2c141#define TEGRA234_SID_SES_SE0 0x2d142#define TEGRA234_SID_SES_SE1 0x2e143#define TEGRA234_SID_SES_SE2 0x2f144#define TEGRA234_SID_SEU1_SE0 0x30145#define TEGRA234_SID_SEU1_SE1 0x31146#define TEGRA234_SID_SEU1_SE2 0x32147#define TEGRA234_SID_TSEC 0x33148#define TEGRA234_SID_VIC 0x34149#define TEGRA234_SID_HC_VM0 0x3d150#define TEGRA234_SID_HC_VM1 0x3e151#define TEGRA234_SID_HC_VM2 0x3f152#define TEGRA234_SID_HC_VM3 0x40153#define TEGRA234_SID_HC_VM4 0x41154#define TEGRA234_SID_HC_VM5 0x42155#define TEGRA234_SID_HC_VM6 0x43156#define TEGRA234_SID_HC_VM7 0x44157#define TEGRA234_SID_SE_VM0 0x45158#define TEGRA234_SID_SE_VM1 0x46159#define TEGRA234_SID_SE_VM2 0x47160#define TEGRA234_SID_ISPFALC 0x48161#define TEGRA234_SID_NISO1_SMMU_TEST 0x49162#define TEGRA234_SID_TSEC_VM0 0x4a163 164/* Shared stream IDs */165#define TEGRA234_SID_HOST1X_CTX0 0x35166#define TEGRA234_SID_HOST1X_CTX1 0x36167#define TEGRA234_SID_HOST1X_CTX2 0x37168#define TEGRA234_SID_HOST1X_CTX3 0x38169#define TEGRA234_SID_HOST1X_CTX4 0x39170#define TEGRA234_SID_HOST1X_CTX5 0x3a171#define TEGRA234_SID_HOST1X_CTX6 0x3b172#define TEGRA234_SID_HOST1X_CTX7 0x3c173 174/*175 * memory client IDs176 */177 178/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */179#define TEGRA234_MEMORY_CLIENT_PTCR 0x00180/* MSS internal memqual MIU7 read clients */181#define TEGRA234_MEMORY_CLIENT_MIU7R 0x01182/* MSS internal memqual MIU7 write clients */183#define TEGRA234_MEMORY_CLIENT_MIU7W 0x02184/* MSS internal memqual MIU8 read clients */185#define TEGRA234_MEMORY_CLIENT_MIU8R 0x03186/* MSS internal memqual MIU8 write clients */187#define TEGRA234_MEMORY_CLIENT_MIU8W 0x04188/* MSS internal memqual MIU9 read clients */189#define TEGRA234_MEMORY_CLIENT_MIU9R 0x05190/* MSS internal memqual MIU9 write clients */191#define TEGRA234_MEMORY_CLIENT_MIU9W 0x06192/* MSS internal memqual MIU10 read clients */193#define TEGRA234_MEMORY_CLIENT_MIU10R 0x07194/* MSS internal memqual MIU10 write clients */195#define TEGRA234_MEMORY_CLIENT_MIU10W 0x08196/* MSS internal memqual MIU11 read clients */197#define TEGRA234_MEMORY_CLIENT_MIU11R 0x09198/* MSS internal memqual MIU11 write clients */199#define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a200/* MSS internal memqual MIU12 read clients */201#define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b202/* MSS internal memqual MIU12 write clients */203#define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c204/* MSS internal memqual MIU13 read clients */205#define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d206/* MSS internal memqual MIU13 write clients */207#define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e208#define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13209#define TEGRA234_MEMORY_CLIENT_NVL5R 0x14210/* High-definition audio (HDA) read clients */211#define TEGRA234_MEMORY_CLIENT_HDAR 0x15212/* Host channel data read clients */213#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16214#define TEGRA234_MEMORY_CLIENT_NVL5W 0x17215#define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18216#define TEGRA234_MEMORY_CLIENT_NVL6R 0x19217#define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a218#define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b219#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c220#define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d221#define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e222#define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20223#define TEGRA234_MEMORY_CLIENT_NVL8R 0x21224#define TEGRA234_MEMORY_CLIENT_NVL8W 0x22225#define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23226#define TEGRA234_MEMORY_CLIENT_NVL9R 0x24227#define TEGRA234_MEMORY_CLIENT_NVL9W 0x25228/* PCIE6 read clients */229#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28230/* PCIE6 write clients */231#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29232/* PCIE7 read clients */233#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a234#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b235/* DLA0ARDB read clients */236#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c237/* DLA0ARDB1 read clients */238#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d239/* DLA0 writes */240#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e241/* DLA1ARDB read clients */242#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f243/* PCIE7 write clients */244#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30245/* PCIE8 read clients */246#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32247/* High-definition audio (HDA) write clients */248#define TEGRA234_MEMORY_CLIENT_HDAW 0x35249/* Writes from Cortex-A9 4 CPU cores via the L2 cache */250#define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39251/* OFAA client */252#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a253/* PCIE8 write clients */254#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b255/* PCIE9 read clients */256#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c257/* PCIE6r1 read clients */258#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d259/* PCIE9 write clients */260#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e261/* PCIE10 read clients */262#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f263/* PCIE10 write clients */264#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40265/* ISP read client for Crossbar A */266#define TEGRA234_MEMORY_CLIENT_ISPRA 0x44267/* ISP read client 1 for Crossbar A */268#define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45269/* ISP Write client for Crossbar A */270#define TEGRA234_MEMORY_CLIENT_ISPWA 0x46271/* ISP Write client Crossbar B */272#define TEGRA234_MEMORY_CLIENT_ISPWB 0x47273/* PCIE10r1 read clients */274#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48275/* PCIE7r1 read clients */276#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49277/* XUSB_HOST read clients */278#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a279/* XUSB_HOST write clients */280#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b281/* XUSB read clients */282#define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c283/* XUSB_DEV write clients */284#define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d285/* TSEC Memory Return Data Client Description */286#define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54287/* TSEC Memory Write Client Description */288#define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55289/* XSPI writes */290#define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56291/* MGBE0 read client */292#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58293/* MGBEB read client */294#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59295/* MGBEC read client */296#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a297/* MGBED read client */298#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b299/* MGBE0 write client */300#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c301/* OFAA client */302#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d303/* OFAA writes */304#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e305/* MGBEB write client */306#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f307/* sdmmca memory read client */308#define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60309/* MGBEC write client */310#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61311/* sdmmcd memory read client */312#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63313/* sdmmca memory write client */314#define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64315/* MGBED write client */316#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65317/* sdmmcd memory write client */318#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67319/* SE Memory Return Data Client Description */320#define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68321/* SE Memory Write Client Description */322#define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69323#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c324#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d325/* DLA1ARDB1 read clients */326#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e327/* DLA1 writes */328#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f329/* VI FLACON read clients */330#define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71331/* VI Write client */332#define TEGRA234_MEMORY_CLIENT_VI2W 0x70333/* VI Write client */334#define TEGRA234_MEMORY_CLIENT_VIW 0x72335/* NISO display read client */336#define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73337/* NVDISPNISO writes */338#define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74339/* XSPI client */340#define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75341/* XSPI writes */342#define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76343/* XSPI client */344#define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77345#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78346#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79347/* Audio Processing (APE) engine read clients */348#define TEGRA234_MEMORY_CLIENT_APER 0x7a349/* Audio Processing (APE) engine write clients */350#define TEGRA234_MEMORY_CLIENT_APEW 0x7b351/* VI2FAL writes */352#define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c353#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e354#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f355/* SE Memory Return Data Client Description */356#define TEGRA234_MEMORY_CLIENT_SESRD 0x80357/* SE Memory Write Client Description */358#define TEGRA234_MEMORY_CLIENT_SESWR 0x81359/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */360#define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82361/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */362#define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83363/* ETR read clients */364#define TEGRA234_MEMORY_CLIENT_ETRR 0x84365/* ETR write clients */366#define TEGRA234_MEMORY_CLIENT_ETRW 0x85367/* AXI Switch read client */368#define TEGRA234_MEMORY_CLIENT_AXISR 0x8c369/* AXI Switch write client */370#define TEGRA234_MEMORY_CLIENT_AXISW 0x8d371/* EQOS read client */372#define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e373/* EQOS write client */374#define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f375/* UFSHC read client */376#define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90377/* UFSHC write client */378#define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91379/* NVDISPLAY read client */380#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92381/* BPMP read client */382#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93383/* BPMP write client */384#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94385/* BPMPDMA read client */386#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95387/* BPMPDMA write client */388#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96389/* AON read client */390#define TEGRA234_MEMORY_CLIENT_AONR 0x97391/* AON write client */392#define TEGRA234_MEMORY_CLIENT_AONW 0x98393/* AONDMA read client */394#define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99395/* AONDMA write client */396#define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a397/* SCE read client */398#define TEGRA234_MEMORY_CLIENT_SCER 0x9b399/* SCE write client */400#define TEGRA234_MEMORY_CLIENT_SCEW 0x9c401/* SCEDMA read client */402#define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d403/* SCEDMA write client */404#define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e405/* APEDMA read client */406#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f407/* APEDMA write client */408#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0409/* NVDISPLAY read client instance 2 */410#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1411#define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2412/* MSS internal memqual MIU0 read clients */413#define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6414/* MSS internal memqual MIU0 write clients */415#define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7416/* MSS internal memqual MIU1 read clients */417#define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8418/* MSS internal memqual MIU1 write clients */419#define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9420/* MSS internal memqual MIU2 read clients */421#define TEGRA234_MEMORY_CLIENT_MIU2R 0xae422/* MSS internal memqual MIU2 write clients */423#define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf424/* MSS internal memqual MIU3 read clients */425#define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0426/* MSS internal memqual MIU3 write clients */427#define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1428/* MSS internal memqual MIU4 read clients */429#define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2430/* MSS internal memqual MIU4 write clients */431#define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3432#define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4433#define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5434#define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6435#define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7436#define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8437#define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9438#define TEGRA234_MEMORY_CLIENT_NVL2R 0xba439#define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb440/* VI FLACON read clients */441#define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc442/* VIFAL write clients */443#define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd444/* DLA0ARDA read clients */445#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe446/* DLA0 Falcon read clients */447#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf448/* DLA0 write clients */449#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0450/* DLA0 write clients */451#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1452/* DLA1ARDA read clients */453#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2454/* DLA1 Falcon read clients */455#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3456/* DLA1 write clients */457#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4458/* DLA1 write clients */459#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5460/* PVA0RDA read clients */461#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6462/* PVA0RDB read clients */463#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7464/* PVA0RDC read clients */465#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8466/* PVA0WRA write clients */467#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9468/* PVA0WRB write clients */469#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca470/* PVA0WRC write clients */471#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb472/* RCE read client */473#define TEGRA234_MEMORY_CLIENT_RCER 0xd2474/* RCE write client */475#define TEGRA234_MEMORY_CLIENT_RCEW 0xd3476/* RCEDMA read client */477#define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4478/* RCEDMA write client */479#define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5480/* PCIE0 read clients */481#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8482/* PCIE0 write clients */483#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9484/* PCIE1 read clients */485#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda486/* PCIE1 write clients */487#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb488/* PCIE2 read clients */489#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc490/* PCIE2 write clients */491#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd492/* PCIE3 read clients */493#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde494/* PCIE3 write clients */495#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf496/* PCIE4 read clients */497#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0498/* PCIE4 write clients */499#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1500/* PCIE5 read clients */501#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2502/* PCIE5 write clients */503#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3504/* ISP read client 1 for Crossbar A */505#define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4506#define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5507#define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6508#define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7509#define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8510/* DLA0ARDA1 read clients */511#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9512/* DLA1ARDA1 read clients */513#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea514/* PVA0RDA1 read clients */515#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb516/* PVA0RDB1 read clients */517#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec518/* PCIE5r1 read clients */519#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef520#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0521/* ISP read client for Crossbar A */522#define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2523#define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4524#define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5525#define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6526#define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7527#define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8528/* MSS internal memqual MIU5 read clients */529#define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc530/* MSS internal memqual MIU5 write clients */531#define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd532/* MSS internal memqual MIU6 read clients */533#define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe534/* MSS internal memqual MIU6 write clients */535#define TEGRA234_MEMORY_CLIENT_MIU6W 0xff536#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123537#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124538 539/* ICC ID's for dummy MC clients used to represent CPU Clusters */540#define TEGRA_ICC_MC_CPU_CLUSTER0 1003541#define TEGRA_ICC_MC_CPU_CLUSTER1 1004542#define TEGRA_ICC_MC_CPU_CLUSTER2 1005543 544#endif545