112 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H3#define DT_BINDINGS_MEMORY_TEGRA30_MC_H4 5#define TEGRA_SWGROUP_PTC 06#define TEGRA_SWGROUP_DC 17#define TEGRA_SWGROUP_DCB 28#define TEGRA_SWGROUP_EPP 39#define TEGRA_SWGROUP_G2 410#define TEGRA_SWGROUP_MPE 511#define TEGRA_SWGROUP_VI 612#define TEGRA_SWGROUP_AFI 713#define TEGRA_SWGROUP_AVPC 814#define TEGRA_SWGROUP_NV 915#define TEGRA_SWGROUP_NV2 1016#define TEGRA_SWGROUP_HDA 1117#define TEGRA_SWGROUP_HC 1218#define TEGRA_SWGROUP_PPCS 1319#define TEGRA_SWGROUP_SATA 1420#define TEGRA_SWGROUP_VDE 1521#define TEGRA_SWGROUP_MPCORELP 1622#define TEGRA_SWGROUP_MPCORE 1723#define TEGRA_SWGROUP_ISP 1824 25#define TEGRA30_MC_RESET_AFI 026#define TEGRA30_MC_RESET_AVPC 127#define TEGRA30_MC_RESET_DC 228#define TEGRA30_MC_RESET_DCB 329#define TEGRA30_MC_RESET_EPP 430#define TEGRA30_MC_RESET_2D 531#define TEGRA30_MC_RESET_HC 632#define TEGRA30_MC_RESET_HDA 733#define TEGRA30_MC_RESET_ISP 834#define TEGRA30_MC_RESET_MPCORE 935#define TEGRA30_MC_RESET_MPCORELP 1036#define TEGRA30_MC_RESET_MPE 1137#define TEGRA30_MC_RESET_3D 1238#define TEGRA30_MC_RESET_3D2 1339#define TEGRA30_MC_RESET_PPCS 1440#define TEGRA30_MC_RESET_SATA 1541#define TEGRA30_MC_RESET_VDE 1642#define TEGRA30_MC_RESET_VI 1743 44#define TEGRA30_MC_PTCR 045#define TEGRA30_MC_DISPLAY0A 146#define TEGRA30_MC_DISPLAY0AB 247#define TEGRA30_MC_DISPLAY0B 348#define TEGRA30_MC_DISPLAY0BB 449#define TEGRA30_MC_DISPLAY0C 550#define TEGRA30_MC_DISPLAY0CB 651#define TEGRA30_MC_DISPLAY1B 752#define TEGRA30_MC_DISPLAY1BB 853#define TEGRA30_MC_EPPUP 954#define TEGRA30_MC_G2PR 1055#define TEGRA30_MC_G2SR 1156#define TEGRA30_MC_MPEUNIFBR 1257#define TEGRA30_MC_VIRUV 1358#define TEGRA30_MC_AFIR 1459#define TEGRA30_MC_AVPCARM7R 1560#define TEGRA30_MC_DISPLAYHC 1661#define TEGRA30_MC_DISPLAYHCB 1762#define TEGRA30_MC_FDCDRD 1863#define TEGRA30_MC_FDCDRD2 1964#define TEGRA30_MC_G2DR 2065#define TEGRA30_MC_HDAR 2166#define TEGRA30_MC_HOST1XDMAR 2267#define TEGRA30_MC_HOST1XR 2368#define TEGRA30_MC_IDXSRD 2469#define TEGRA30_MC_IDXSRD2 2570#define TEGRA30_MC_MPE_IPRED 2671#define TEGRA30_MC_MPEAMEMRD 2772#define TEGRA30_MC_MPECSRD 2873#define TEGRA30_MC_PPCSAHBDMAR 2974#define TEGRA30_MC_PPCSAHBSLVR 3075#define TEGRA30_MC_SATAR 3176#define TEGRA30_MC_TEXSRD 3277#define TEGRA30_MC_TEXSRD2 3378#define TEGRA30_MC_VDEBSEVR 3479#define TEGRA30_MC_VDEMBER 3580#define TEGRA30_MC_VDEMCER 3681#define TEGRA30_MC_VDETPER 3782#define TEGRA30_MC_MPCORELPR 3883#define TEGRA30_MC_MPCORER 3984#define TEGRA30_MC_EPPU 4085#define TEGRA30_MC_EPPV 4186#define TEGRA30_MC_EPPY 4287#define TEGRA30_MC_MPEUNIFBW 4388#define TEGRA30_MC_VIWSB 4489#define TEGRA30_MC_VIWU 4590#define TEGRA30_MC_VIWV 4691#define TEGRA30_MC_VIWY 4792#define TEGRA30_MC_G2DW 4893#define TEGRA30_MC_AFIW 4994#define TEGRA30_MC_AVPCARM7W 5095#define TEGRA30_MC_FDCDWR 5196#define TEGRA30_MC_FDCDWR2 5297#define TEGRA30_MC_HDAW 5398#define TEGRA30_MC_HOST1XW 5499#define TEGRA30_MC_ISPW 55100#define TEGRA30_MC_MPCORELPW 56101#define TEGRA30_MC_MPCOREW 57102#define TEGRA30_MC_MPECSWR 58103#define TEGRA30_MC_PPCSAHBDMAW 59104#define TEGRA30_MC_PPCSAHBSLVW 60105#define TEGRA30_MC_SATAW 61106#define TEGRA30_MC_VDEBSEVW 62107#define TEGRA30_MC_VDEDBGW 63108#define TEGRA30_MC_VDEMBEW 64109#define TEGRA30_MC_VDETPMW 65110 111#endif112