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1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */2/*3 * Device Tree constants for the Texas Instruments DP83867 PHY4 *5 * Author: Dan Murphy <dmurphy@ti.com>6 *7 * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/8 */9 10#ifndef _DT_BINDINGS_TI_DP83867_H11#define _DT_BINDINGS_TI_DP83867_H12 13/* PHY CTRL bits */14#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x0015#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x0116#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x0217#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x0318 19/* RGMIIDCTL internal delay for rx and tx */20#define DP83867_RGMIIDCTL_250_PS 0x021#define DP83867_RGMIIDCTL_500_PS 0x122#define DP83867_RGMIIDCTL_750_PS 0x223#define DP83867_RGMIIDCTL_1_NS 0x324#define DP83867_RGMIIDCTL_1_25_NS 0x425#define DP83867_RGMIIDCTL_1_50_NS 0x526#define DP83867_RGMIIDCTL_1_75_NS 0x627#define DP83867_RGMIIDCTL_2_00_NS 0x728#define DP83867_RGMIIDCTL_2_25_NS 0x829#define DP83867_RGMIIDCTL_2_50_NS 0x930#define DP83867_RGMIIDCTL_2_75_NS 0xa31#define DP83867_RGMIIDCTL_3_00_NS 0xb32#define DP83867_RGMIIDCTL_3_25_NS 0xc33#define DP83867_RGMIIDCTL_3_50_NS 0xd34#define DP83867_RGMIIDCTL_3_75_NS 0xe35#define DP83867_RGMIIDCTL_4_00_NS 0xf36 37/* IO_MUX_CFG - Clock output selection */38#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x039#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x140#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x241#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x342#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x443#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x544#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x645#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x746#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x847#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x948#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA49#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB50#define DP83867_CLK_O_SEL_REF_CLK 0xC51/* Special flag to indicate clock should be off */52#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF53#endif54