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1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */2/*3 * Device Tree constants for the Texas Instruments DP83869 PHY4 *5 * Author: Dan Murphy <dmurphy@ti.com>6 *7 * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/8 */9 10#ifndef _DT_BINDINGS_TI_DP83869_H11#define _DT_BINDINGS_TI_DP83869_H12 13/* PHY CTRL bits */14#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x0015#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x0116#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x0217#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x0318 19/* IO_MUX_CFG - Clock output selection */20#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x021#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x122#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x223#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x324#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x425#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x526#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x627#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x728#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x829#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x930#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa31#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb32#define DP83869_CLK_O_SEL_REF_CLK 0xc33 34#define DP83869_RGMII_COPPER_ETHERNET 0x0035#define DP83869_RGMII_1000_BASE 0x0136#define DP83869_RGMII_100_BASE 0x0237#define DP83869_RGMII_SGMII_BRIDGE 0x0338#define DP83869_1000M_MEDIA_CONVERT 0x0439#define DP83869_100M_MEDIA_CONVERT 0x0540#define DP83869_SGMII_COPPER_ETHERNET 0x0641 42#endif43