18 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * MIO pin configuration defines for Xilinx Zynq4 *5 * Copyright (C) 2021 Xilinx, Inc.6 */7 8#ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H9#define _DT_BINDINGS_PINCTRL_ZYNQ_H10 11/* Configuration options for different power supplies */12#define IO_STANDARD_LVCMOS18 113#define IO_STANDARD_LVCMOS25 214#define IO_STANDARD_LVCMOS33 315#define IO_STANDARD_HSTL 416 17#endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */18