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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * MIO pin configuration defines for Xilinx ZynqMP4 *5 * Copyright (C) 2020 Xilinx, Inc.6 */7 8#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H9#define _DT_BINDINGS_PINCTRL_ZYNQMP_H10 11/* Bit value for different voltage levels */12#define IO_STANDARD_LVCMOS33 013#define IO_STANDARD_LVCMOS18 114 15/* Bit values for Slew Rates */16#define SLEW_RATE_FAST 017#define SLEW_RATE_SLOW 118 19#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */20