46 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (C) 2018 Xilinx, Inc.4 */5 6#ifndef _DT_BINDINGS_ZYNQMP_POWER_H7#define _DT_BINDINGS_ZYNQMP_POWER_H8 9#define PD_RPU_0 710#define PD_RPU_1 811#define PD_R5_0_ATCM 1512#define PD_R5_0_BTCM 1613#define PD_R5_1_ATCM 1714#define PD_R5_1_BTCM 1815#define PD_USB_0 2216#define PD_USB_1 2317#define PD_TTC_0 2418#define PD_TTC_1 2519#define PD_TTC_2 2620#define PD_TTC_3 2721#define PD_SATA 2822#define PD_ETH_0 2923#define PD_ETH_1 3024#define PD_ETH_2 3125#define PD_ETH_3 3226#define PD_UART_0 3327#define PD_UART_1 3428#define PD_SPI_0 3529#define PD_SPI_1 3630#define PD_I2C_0 3731#define PD_I2C_1 3832#define PD_SD_0 3933#define PD_SD_1 4034#define PD_DP 4135#define PD_GDMA 4236#define PD_ADMA 4337#define PD_NAND 4438#define PD_QSPI 4539#define PD_GPIO 4640#define PD_CAN_0 4741#define PD_CAN_1 4842#define PD_GPU 5843#define PD_PCIE 5944 45#endif46