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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Device Tree binding constants for Actions Semi S500 Reset Management Unit4 *5 * Copyright (c) 2014 Actions Semi Inc.6 * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>7 */8 9#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H10#define __DT_BINDINGS_ACTIONS_S500_RESET_H11 12#define RESET_DMAC 013#define RESET_NORIF 114#define RESET_DDR 215#define RESET_NANDC 316#define RESET_SD0 417#define RESET_SD1 518#define RESET_PCM1 619#define RESET_DE 720#define RESET_LCD 821#define RESET_SD2 922#define RESET_DSI 1023#define RESET_CSI 1124#define RESET_BISP 1225#define RESET_KEY 1326#define RESET_GPIO 1427#define RESET_AUDIO 1528#define RESET_PCM0 1629#define RESET_VDE 1730#define RESET_VCE 1831#define RESET_GPU3D 1932#define RESET_NIC301 2033#define RESET_LENS 2134#define RESET_PERIPHRESET 2235#define RESET_USB2_0 2336#define RESET_TVOUT 2437#define RESET_HDMI 2538#define RESET_HDCP2TX 2639#define RESET_UART6 2740#define RESET_UART0 2841#define RESET_UART1 2942#define RESET_UART2 3043#define RESET_SPI0 3144#define RESET_SPI1 3245#define RESET_SPI2 3346#define RESET_SPI3 3447#define RESET_I2C0 3548#define RESET_I2C1 3649#define RESET_USB3 3750#define RESET_UART3 3851#define RESET_UART4 3952#define RESET_UART5 4053#define RESET_I2C2 4154#define RESET_I2C3 4255#define RESET_ETHERNET 4356#define RESET_CHIPID 4457#define RESET_USB2_1 4558#define RESET_WD0RESET 4659#define RESET_WD1RESET 4760#define RESET_WD2RESET 4861#define RESET_WD3RESET 4962#define RESET_DBG0RESET 5063#define RESET_DBG1RESET 5164#define RESET_DBG2RESET 5265#define RESET_DBG3RESET 5366 67#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */68