103 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>4 */5 6#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H7#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H8 9/* MPUMODRST */10#define CPU0_RESET 011#define CPU1_RESET 112#define WDS_RESET 213#define SCUPER_RESET 314 15/* PER0MODRST */16#define EMAC0_RESET 3217#define EMAC1_RESET 3318#define EMAC2_RESET 3419#define USB0_RESET 3520#define USB1_RESET 3621#define NAND_RESET 3722#define QSPI_RESET 3823#define SDMMC_RESET 3924#define EMAC0_OCP_RESET 4025#define EMAC1_OCP_RESET 4126#define EMAC2_OCP_RESET 4227#define USB0_OCP_RESET 4328#define USB1_OCP_RESET 4429#define NAND_OCP_RESET 4530#define QSPI_OCP_RESET 4631#define SDMMC_OCP_RESET 4732#define DMA_RESET 4833#define SPIM0_RESET 4934#define SPIM1_RESET 5035#define SPIS0_RESET 5136#define SPIS1_RESET 5237#define DMA_OCP_RESET 5338#define EMAC_PTP_RESET 5439/* 55 is empty*/40#define DMAIF0_RESET 5641#define DMAIF1_RESET 5742#define DMAIF2_RESET 5843#define DMAIF3_RESET 5944#define DMAIF4_RESET 6045#define DMAIF5_RESET 6146#define DMAIF6_RESET 6247#define DMAIF7_RESET 6348 49/* PER1MODRST */50#define L4WD0_RESET 6451#define L4WD1_RESET 6552#define L4SYSTIMER0_RESET 6653#define L4SYSTIMER1_RESET 6754#define SPTIMER0_RESET 6855#define SPTIMER1_RESET 6956/* 70-71 is reserved */57#define I2C0_RESET 7258#define I2C1_RESET 7359#define I2C2_RESET 7460#define I2C3_RESET 7561#define I2C4_RESET 7662/* 77-79 is reserved */63#define UART0_RESET 8064#define UART1_RESET 8165/* 82-87 is reserved */66#define GPIO0_RESET 8867#define GPIO1_RESET 8968#define GPIO2_RESET 9069 70/* BRGMODRST */71#define HPS2FPGA_RESET 9672#define LWHPS2FPGA_RESET 9773#define FPGA2HPS_RESET 9874#define F2SSDRAM0_RESET 9975#define F2SSDRAM1_RESET 10076#define F2SSDRAM2_RESET 10177#define DDRSCH_RESET 10278 79/* SYSMODRST*/80#define ROM_RESET 12881#define OCRAM_RESET 12982/* 130 is reserved */83#define FPGAMGR_RESET 13184#define S2F_RESET 13285#define SYSDBG_RESET 13386#define OCRAM_OCP_RESET 13487 88/* COLDMODRST */89#define CLKMGRCOLD_RESET 16090/* 161-162 is reserved */91#define S2FCOLD_RESET 16392#define TIMESTAMPCOLD_RESET 16493#define TAPCOLD_RESET 16594#define HMCCOLD_RESET 16695#define IOMGRCOLD_RESET 16796 97/* NRSTMODRST */98#define NRSTPINOE_RESET 19299 100/* DBGMODRST */101#define DBG_RESET 224102#endif103