101 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2016 Intel Corporation. All rights reserved4 * Copyright (C) 2016 Altera Corporation. All rights reserved5 *6 * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"7 */8 9#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H10#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H11 12/* MPUMODRST */13#define CPU0_RESET 014#define CPU1_RESET 115#define CPU2_RESET 216#define CPU3_RESET 317 18/* PER0MODRST */19#define EMAC0_RESET 3220#define EMAC1_RESET 3321#define EMAC2_RESET 3422#define USB0_RESET 3523#define USB1_RESET 3624#define NAND_RESET 3725/* 38 is empty */26#define SDMMC_RESET 3927#define EMAC0_OCP_RESET 4028#define EMAC1_OCP_RESET 4129#define EMAC2_OCP_RESET 4230#define USB0_OCP_RESET 4331#define USB1_OCP_RESET 4432#define NAND_OCP_RESET 4533/* 46 is empty */34#define SDMMC_OCP_RESET 4735#define DMA_RESET 4836#define SPIM0_RESET 4937#define SPIM1_RESET 5038#define SPIS0_RESET 5139#define SPIS1_RESET 5240#define DMA_OCP_RESET 5341#define EMAC_PTP_RESET 5442/* 55 is empty*/43#define DMAIF0_RESET 5644#define DMAIF1_RESET 5745#define DMAIF2_RESET 5846#define DMAIF3_RESET 5947#define DMAIF4_RESET 6048#define DMAIF5_RESET 6149#define DMAIF6_RESET 6250#define DMAIF7_RESET 6351 52/* PER1MODRST */53#define WATCHDOG0_RESET 6454#define WATCHDOG1_RESET 6555#define WATCHDOG2_RESET 6656#define WATCHDOG3_RESET 6757#define L4SYSTIMER0_RESET 6858#define L4SYSTIMER1_RESET 6959#define SPTIMER0_RESET 7060#define SPTIMER1_RESET 7161#define I2C0_RESET 7262#define I2C1_RESET 7363#define I2C2_RESET 7464#define I2C3_RESET 7565#define I2C4_RESET 7666#define I3C0_RESET 7767#define I3C1_RESET 7868/* 79 is empty */69#define UART0_RESET 8070#define UART1_RESET 8171/* 82-87 is empty */72#define GPIO0_RESET 8873#define GPIO1_RESET 8974#define WATCHDOG4_RESET 9075 76/* BRGMODRST */77#define SOC2FPGA_RESET 9678#define LWHPS2FPGA_RESET 9779#define FPGA2SOC_RESET 9880#define F2SSDRAM0_RESET 9981#define F2SSDRAM1_RESET 10082#define F2SSDRAM2_RESET 10183#define DDRSCH_RESET 10284 85/* COLDMODRST */86#define CPUPO0_RESET 16087#define CPUPO1_RESET 16188#define CPUPO2_RESET 16289#define CPUPO3_RESET 16390/* 164-167 is empty */91#define L2_RESET 16892 93/* DBGMODRST */94#define DBG_RESET 22495#define CSDAP_RESET 22596 97/* TAPMODRST */98#define TAP_RESET 25699 100#endif101