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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>4 */5 6#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H7#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H8 9/* MPUMODRST */10#define CPU0_RESET 011#define CPU1_RESET 112#define WDS_RESET 213#define SCUPER_RESET 314#define L2_RESET 415 16/* PERMODRST */17#define EMAC0_RESET 3218#define EMAC1_RESET 3319#define USB0_RESET 3420#define USB1_RESET 3521#define NAND_RESET 3622#define QSPI_RESET 3723#define L4WD0_RESET 3824#define L4WD1_RESET 3925#define OSC1TIMER0_RESET 4026#define OSC1TIMER1_RESET 4127#define SPTIMER0_RESET 4228#define SPTIMER1_RESET 4329#define I2C0_RESET 4430#define I2C1_RESET 4531#define I2C2_RESET 4632#define I2C3_RESET 4733#define UART0_RESET 4834#define UART1_RESET 4935#define SPIM0_RESET 5036#define SPIM1_RESET 5137#define SPIS0_RESET 5238#define SPIS1_RESET 5339#define SDMMC_RESET 5440#define CAN0_RESET 5541#define CAN1_RESET 5642#define GPIO0_RESET 5743#define GPIO1_RESET 5844#define GPIO2_RESET 5945#define DMA_RESET 6046#define SDR_RESET 6147 48/* PER2MODRST */49#define DMAIF0_RESET 6450#define DMAIF1_RESET 6551#define DMAIF2_RESET 6652#define DMAIF3_RESET 6753#define DMAIF4_RESET 6854#define DMAIF5_RESET 6955#define DMAIF6_RESET 7056#define DMAIF7_RESET 7157 58/* BRGMODRST */59#define HPS2FPGA_RESET 9660#define LWHPS2FPGA_RESET 9761#define FPGA2HPS_RESET 9862 63/* MISCMODRST*/64#define ROM_RESET 12865#define OCRAM_RESET 12966#define SYSMGR_RESET 13067#define SYSMGRCOLD_RESET 13168#define FPGAMGR_RESET 13269#define ACPIDMAP_RESET 13370#define S2F_RESET 13471#define S2FCOLD_RESET 13572#define NRSTPIN_RESET 13673#define TIMESTAMPCOLD_RESET 13774#define CLKMGRCOLD_RESET 13875#define SCANMGR_RESET 13976#define FRZCTRLCOLD_RESET 14077#define SYSDBG_RESET 14178#define DBG_RESET 14279#define TAPCOLD_RESET 14380#define SDRCOLD_RESET 14481 82#endif83