120 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */2/*3 * Copyright (c) 2023 Amlogic, Inc. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_AMLOGIC_C3_RESET_H7#define _DT_BINDINGS_AMLOGIC_C3_RESET_H8 9/* RESET0 */10/* 0-3 */11#define RESET_USBCTRL 412/* 5-7 */13#define RESET_USBPHY20 814/* 9 */15#define RESET_USB2DRD 1016#define RESET_MIPI_DSI_HOST 1117#define RESET_MIPI_DSI_PHY 1218/* 13-20 */19#define RESET_GE2D 2120#define RESET_DWAP 2221/* 23-31 */22 23/* RESET1 */24#define RESET_AUDIO 3225/* 33-34 */26#define RESET_DDRAPB 3527#define RESET_DDR 3628#define RESET_DOS_CAPB3 3729#define RESET_DOS 3830/* 39-46 */31#define RESET_NNA 4732#define RESET_ETHERNET 4833#define RESET_ISP 4934#define RESET_VC9000E_APB 5035#define RESET_VC9000E_A 5136/* 52 */37#define RESET_VC9000E_CORE 5338/* 54-63 */39 40/* RESET2 */41#define RESET_ABUS_ARB 6442#define RESET_IRCTRL 6543/* 66 */44#define RESET_TEMP_PII 6745/* 68-72 */46#define RESET_SPICC_0 7347#define RESET_SPICC_1 7448#define RESET_RSA 7549 50/* 76-79 */51#define RESET_MSR_CLK 8052#define RESET_SPIFC 8153#define RESET_SAR_ADC 8254/* 83-87 */55#define RESET_ACODEC 8856/* 89-90 */57#define RESET_WATCHDOG 9158/* 92-95 */59 60/* RESET3 */61#define RESET_ISP_NIC_GPV 9662#define RESET_ISP_NIC_MAIN 9763#define RESET_ISP_NIC_VCLK 9864#define RESET_ISP_NIC_VOUT 9965#define RESET_ISP_NIC_ALL 10066#define RESET_VOUT 10167#define RESET_VOUT_VENC 10268/* 103 */69#define RESET_CVE_NIC_GPV 10470#define RESET_CVE_NIC_MAIN 10571#define RESET_CVE_NIC_GE2D 10672#define RESET_CVE_NIC_DW 10673#define RESET_CVE_NIC_CVE 10874#define RESET_CVE_NIC_ALL 10975#define RESET_CVE 11076/* 112-127 */77 78/* RESET4 */79#define RESET_RTC 12880#define RESET_PWM_AB 12981#define RESET_PWM_CD 13082#define RESET_PWM_EF 13183#define RESET_PWM_GH 13284#define RESET_PWM_IJ 13385#define RESET_PWM_KL 13486#define RESET_PWM_MN 13587/* 136-137 */88#define RESET_UART_A 13889#define RESET_UART_B 13990#define RESET_UART_C 14091#define RESET_UART_D 14192#define RESET_UART_E 14293#define RESET_UART_F 14394#define RESET_I2C_S_A 14495#define RESET_I2C_M_A 14596#define RESET_I2C_M_B 14697#define RESET_I2C_M_C 14798#define RESET_I2C_M_D 14899/* 149-151 */100#define RESET_SD_EMMC_A 152101#define RESET_SD_EMMC_B 153102#define RESET_SD_EMMC_C 154103 104/* RESET5 */105/* 160-172 */106#define RESET_BRG_NIC_NNA 173107#define RESET_BRG_MUX_NIC_MAIN 174108#define RESET_BRG_AO_NIC_ALL 175109/* 176-183 */110#define RESET_BRG_NIC_VAPB 184111#define RESET_BRG_NIC_SDIO_B 185112#define RESET_BRG_NIC_SDIO_A 186113#define RESET_BRG_NIC_EMMC 187114#define RESET_BRG_NIC_DSU 188115#define RESET_BRG_NIC_SYSCLK 189116#define RESET_BRG_NIC_MAIN 190117#define RESET_BRG_NIC_ALL 191118 119#endif120