124 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */2/*3 * Copyright (c) 2016 BayLibre, SAS.4 * Author: Neil Armstrong <narmstrong@baylibre.com>5 *6 * Copyright (c) 2017 Amlogic, inc.7 * Author: Yixun Lan <yixun.lan@amlogic.com>8 *9 */10 11#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H12#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H13 14/* RESET0 */15#define RESET_HIU 016#define RESET_PCIE_A 117#define RESET_PCIE_B 218#define RESET_DDR_TOP 319/* 4 */20#define RESET_VIU 521#define RESET_PCIE_PHY 622#define RESET_PCIE_APB 723/* 8 */24/* 9 */25#define RESET_VENC 1026#define RESET_ASSIST 1127/* 12 */28#define RESET_VCBUS 1329/* 14 */30/* 15 */31#define RESET_GIC 1632#define RESET_CAPB3_DECODE 1733/* 18-21 */34#define RESET_SYS_CPU_CAPB3 2235#define RESET_CBUS_CAPB3 2336#define RESET_AHB_CNTL 2437#define RESET_AHB_DATA 2538#define RESET_VCBUS_CLK81 2639#define RESET_MMC 2740/* 28-31 */41/* RESET1 */42/* 32 */43/* 33 */44#define RESET_USB_OTG 3445#define RESET_DDR 3546#define RESET_AO_RESET 3647/* 37 */48#define RESET_AHB_SRAM 3849/* 39 */50/* 40 */51#define RESET_DMA 4152#define RESET_ISA 4253#define RESET_ETHERNET 4354/* 44 */55#define RESET_SD_EMMC_B 4556#define RESET_SD_EMMC_C 4657#define RESET_ROM_BOOT 4758#define RESET_SYS_CPU_0 4859#define RESET_SYS_CPU_1 4960#define RESET_SYS_CPU_2 5061#define RESET_SYS_CPU_3 5162#define RESET_SYS_CPU_CORE_0 5263#define RESET_SYS_CPU_CORE_1 5364#define RESET_SYS_CPU_CORE_2 5465#define RESET_SYS_CPU_CORE_3 5566#define RESET_SYS_PLL_DIV 5667#define RESET_SYS_CPU_AXI 5768#define RESET_SYS_CPU_L2 5869#define RESET_SYS_CPU_P 5970#define RESET_SYS_CPU_MBIST 6071/* 61-63 */72/* RESET2 */73/* 64 */74/* 65 */75#define RESET_AUDIO 6676/* 67 */77#define RESET_MIPI_HOST 6878#define RESET_AUDIO_LOCKER 6979#define RESET_GE2D 7080/* 71-76 */81#define RESET_AO_CPU_RESET 7782/* 78-95 */83/* RESET3 */84#define RESET_RING_OSCILLATOR 9685/* 97-127 */86/* RESET4 */87/* 128 */88/* 129 */89#define RESET_MIPI_PHY 13090/* 131-140 */91#define RESET_VENCL 14192#define RESET_I2C_MASTER_2 14293#define RESET_I2C_MASTER_1 14394/* 144-159 */95/* RESET5 */96/* 160-191 */97/* RESET6 */98#define RESET_PERIPHS_GENERAL 19299#define RESET_PERIPHS_SPICC 193100/* 194 */101/* 195 */102#define RESET_PERIPHS_I2C_MASTER_0 196103/* 197-200 */104#define RESET_PERIPHS_UART_0 201105#define RESET_PERIPHS_UART_1 202106/* 203-204 */107#define RESET_PERIPHS_SPI_0 205108#define RESET_PERIPHS_I2C_MASTER_3 206109/* 207-223 */110/* RESET7 */111#define RESET_USB_DDR_0 224112#define RESET_USB_DDR_1 225113#define RESET_USB_DDR_2 226114#define RESET_USB_DDR_3 227115/* 228 */116#define RESET_DEVICE_MMC_ARB 229117/* 230 */118#define RESET_VID_LOCK 231119#define RESET_A9_DMC_PIPEL 232120#define RESET_DMC_VPU_PIPEL 233121/* 234-255 */122 123#endif124