140 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */2/*3 * Copyright (c) 2019 BayLibre, SAS.4 * Author: Jerome Brunet <jbrunet@baylibre.com>5 *6 */7 8#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H9#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H10 11/* RESET0 */12#define RESET_HIU 013/* 1 */14#define RESET_DOS 215/* 3-4 */16#define RESET_VIU 517#define RESET_AFIFO 618#define RESET_VID_PLL_DIV 719/* 8-9 */20#define RESET_VENC 1021#define RESET_ASSIST 1122#define RESET_PCIE_CTRL_A 1223#define RESET_VCBUS 1324#define RESET_PCIE_PHY 1425#define RESET_PCIE_APB 1526#define RESET_GIC 1627#define RESET_CAPB3_DECODE 1728/* 18 */29#define RESET_HDMITX_CAPB3 1930#define RESET_DVALIN_CAPB3 2031#define RESET_DOS_CAPB3 2132/* 22 */33#define RESET_CBUS_CAPB3 2334#define RESET_AHB_CNTL 2435#define RESET_AHB_DATA 2536#define RESET_VCBUS_CLK81 2637/* 27-31 */38/* RESET1 */39/* 32 */40#define RESET_DEMUX 3341#define RESET_USB 3442#define RESET_DDR 3543/* 36 */44#define RESET_BT656 3745#define RESET_AHB_SRAM 3846/* 39 */47#define RESET_PARSER 4048/* 41 */49#define RESET_ISA 4250#define RESET_ETHERNET 4351#define RESET_SD_EMMC_A 4452#define RESET_SD_EMMC_B 4553#define RESET_SD_EMMC_C 4654/* 47 */55#define RESET_USB_PHY20 4856#define RESET_USB_PHY21 4957/* 50-60 */58#define RESET_AUDIO_CODEC 6159/* 62-63 */60/* RESET2 */61/* 64 */62#define RESET_AUDIO 6563#define RESET_HDMITX_PHY 6664/* 67 */65#define RESET_MIPI_DSI_HOST 6866#define RESET_ALOCKER 6967#define RESET_GE2D 7068#define RESET_PARSER_REG 7169#define RESET_PARSER_FETCH 7270#define RESET_CTL 7371#define RESET_PARSER_TOP 7472/* 75 */73#define RESET_NNA 7674/* 77 */75#define RESET_DVALIN 7876#define RESET_HDMITX 7977/* 80-95 */78/* RESET3 */79/* 96-95 */80#define RESET_DEMUX_TOP 10581#define RESET_DEMUX_DES_PL 10682#define RESET_DEMUX_S2P_0 10783#define RESET_DEMUX_S2P_1 10884#define RESET_DEMUX_0 10985#define RESET_DEMUX_1 11086#define RESET_DEMUX_2 11187/* 112-127 */88/* RESET4 */89/* 128-129 */90#define RESET_MIPI_DSI_PHY 13091/* 131-132 */92#define RESET_RDMA 13393#define RESET_VENCI 13494#define RESET_VENCP 13595/* 136 */96#define RESET_VDAC 13797/* 138-139 */98#define RESET_VDI6 14099#define RESET_VENCL 141100#define RESET_I2C_M1 142101#define RESET_I2C_M2 143102/* 144-159 */103/* RESET5 */104/* 160-191 */105/* RESET6 */106#define RESET_GEN 192107#define RESET_SPICC0 193108#define RESET_SC 194109#define RESET_SANA_3 195110#define RESET_I2C_M0 196111#define RESET_TS_PLL 197112#define RESET_SPICC1 198113#define RESET_STREAM 199114#define RESET_TS_CPU 200115#define RESET_UART0 201116#define RESET_UART1_2 202117#define RESET_ASYNC0 203118#define RESET_ASYNC1 204119#define RESET_SPIFC0 205120#define RESET_I2C_M3 206121/* 207-223 */122/* RESET7 */123#define RESET_USB_DDR_0 224124#define RESET_USB_DDR_1 225125#define RESET_USB_DDR_2 226126#define RESET_USB_DDR_3 227127#define RESET_TS_GPU 228128#define RESET_DEVICE_MMC_ARB 229129#define RESET_DVALIN_DMC_PIPL 230130#define RESET_VID_LOCK 231131#define RESET_NIC_DMC_PIPL 232132#define RESET_DMC_VPU_PIPL 233133#define RESET_GE2D_DMC_PIPL 234134#define RESET_HCODEC_DMC_PIPL 235135#define RESET_WAVE420_DMC_PIPL 236136#define RESET_HEVCF_DMC_PIPL 237137/* 238-255 */138 139#endif140