162 lines · c
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */2/*3 * Copyright (c) 2016 BayLibre, SAS.4 * Author: Neil Armstrong <narmstrong@baylibre.com>5 */6#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H7#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H8 9/* RESET0 */10#define RESET_HIU 011/* 1 */12#define RESET_DOS_RESET 213#define RESET_DDR_TOP 314#define RESET_DCU_RESET 415#define RESET_VIU 516#define RESET_AIU 617#define RESET_VID_PLL_DIV 718/* 8 */19#define RESET_PMUX 920#define RESET_VENC 1021#define RESET_ASSIST 1122#define RESET_AFIFO2 1223#define RESET_VCBUS 1324/* 14 */25/* 15 */26#define RESET_GIC 1627#define RESET_CAPB3_DECODE 1728#define RESET_NAND_CAPB3 1829#define RESET_HDMITX_CAPB3 1930#define RESET_MALI_CAPB3 2031#define RESET_DOS_CAPB3 2132#define RESET_SYS_CPU_CAPB3 2233#define RESET_CBUS_CAPB3 2334#define RESET_AHB_CNTL 2435#define RESET_AHB_DATA 2536#define RESET_VCBUS_CLK81 2637#define RESET_MMC 2738#define RESET_MIPI_0 2839#define RESET_MIPI_1 2940#define RESET_MIPI_2 3041#define RESET_MIPI_3 3142/* RESET1 */43#define RESET_CPPM 3244#define RESET_DEMUX 3345#define RESET_USB_OTG 3446#define RESET_DDR 3547#define RESET_AO_RESET 3648#define RESET_BT656 3749#define RESET_AHB_SRAM 3850/* 39 */51#define RESET_PARSER 4052#define RESET_BLKMV 4153#define RESET_ISA 4254#define RESET_ETHERNET 4355#define RESET_SD_EMMC_A 4456#define RESET_SD_EMMC_B 4557#define RESET_SD_EMMC_C 4658#define RESET_ROM_BOOT 4759#define RESET_SYS_CPU_0 4860#define RESET_SYS_CPU_1 4961#define RESET_SYS_CPU_2 5062#define RESET_SYS_CPU_3 5163#define RESET_SYS_CPU_CORE_0 5264#define RESET_SYS_CPU_CORE_1 5365#define RESET_SYS_CPU_CORE_2 5466#define RESET_SYS_CPU_CORE_3 5567#define RESET_SYS_PLL_DIV 5668#define RESET_SYS_CPU_AXI 5769#define RESET_SYS_CPU_L2 5870#define RESET_SYS_CPU_P 5971#define RESET_SYS_CPU_MBIST 6072#define RESET_ACODEC 6173/* 62 */74/* 63 */75/* RESET2 */76#define RESET_VD_RMEM 6477#define RESET_AUDIN 6578#define RESET_HDMI_TX 6679/* 67 */80/* 68 */81/* 69 */82#define RESET_GE2D 7083#define RESET_PARSER_REG 7184#define RESET_PARSER_FETCH 7285#define RESET_PARSER_CTL 7386#define RESET_PARSER_TOP 7487/* 75 */88/* 76 */89#define RESET_AO_CPU_RESET 7790#define RESET_MALI 7891#define RESET_HDMI_SYSTEM_RESET 7992/* 80-95 */93/* RESET3 */94#define RESET_RING_OSCILLATOR 9695#define RESET_SYS_CPU 9796#define RESET_EFUSE 9897#define RESET_SYS_CPU_BVCI 9998#define RESET_AIFIFO 10099#define RESET_TVFE 101100#define RESET_AHB_BRIDGE_CNTL 102101/* 103 */102#define RESET_AUDIO_DAC 104103#define RESET_DEMUX_TOP 105104#define RESET_DEMUX_DES 106105#define RESET_DEMUX_S2P_0 107106#define RESET_DEMUX_S2P_1 108107#define RESET_DEMUX_RESET_0 109108#define RESET_DEMUX_RESET_1 110109#define RESET_DEMUX_RESET_2 111110/* 112-127 */111/* RESET4 */112/* 128 */113/* 129 */114/* 130 */115/* 131 */116#define RESET_DVIN_RESET 132117#define RESET_RDMA 133118#define RESET_VENCI 134119#define RESET_VENCP 135120/* 136 */121#define RESET_VDAC 137122#define RESET_RTC 138123/* 139 */124#define RESET_VDI6 140125#define RESET_VENCL 141126#define RESET_I2C_MASTER_2 142127#define RESET_I2C_MASTER_1 143128/* 144-159 */129/* RESET5 */130/* 160-191 */131/* RESET6 */132#define RESET_PERIPHS_GENERAL 192133#define RESET_PERIPHS_SPICC 193134#define RESET_PERIPHS_SMART_CARD 194135#define RESET_PERIPHS_SAR_ADC 195136#define RESET_PERIPHS_I2C_MASTER_0 196137#define RESET_SANA 197138/* 198 */139#define RESET_PERIPHS_STREAM_INTERFACE 199140#define RESET_PERIPHS_SDIO 200141#define RESET_PERIPHS_UART_0 201142#define RESET_PERIPHS_UART_1_2 202143#define RESET_PERIPHS_ASYNC_0 203144#define RESET_PERIPHS_ASYNC_1 204145#define RESET_PERIPHS_SPI_0 205146#define RESET_PERIPHS_SDHC 206147#define RESET_UART_SLIP 207148/* 208-223 */149/* RESET7 */150#define RESET_USB_DDR_0 224151#define RESET_USB_DDR_1 225152#define RESET_USB_DDR_2 226153#define RESET_USB_DDR_3 227154/* 228 */155#define RESET_DEVICE_MMC_ARB 229156/* 230 */157#define RESET_VID_LOCK 231158#define RESET_A9_DMC_PIPEL 232159/* 233-255 */160 161#endif162