126 lines · c
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */2/*3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.4 * Author: Zelong Dong <zelong.dong@amlogic.com>5 *6 */7 8#ifndef _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H9#define _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H10 11/* RESET0 */12#define RESET_USB_DDR0 013#define RESET_USB_DDR1 114#define RESET_USB_DDR2 215#define RESET_USB_DDR3 316#define RESET_USBCTRL 417/* 5-7 */18#define RESET_USBPHY20 819#define RESET_USBPHY21 920/* 10-15 */21#define RESET_HDMITX_APB 1622#define RESET_BRG_VCBUS_DEC 1723#define RESET_VCBUS 1824#define RESET_VID_PLL_DIV 1925#define RESET_VDI6 2026#define RESET_GE2D 2127#define RESET_HDMITXPHY 2228#define RESET_VID_LOCK 2329#define RESET_VENCL 2430#define RESET_VDAC 2531#define RESET_VENCP 2632#define RESET_VENCI 2733#define RESET_RDMA 2834#define RESET_HDMI_TX 2935#define RESET_VIU 3036#define RESET_VENC 3137 38/* RESET1 */39#define RESET_AUDIO 3240#define RESET_MALI_APB 3341#define RESET_MALI 3442#define RESET_DDR_APB 3543#define RESET_DDR 3644#define RESET_DOS_APB 3745#define RESET_DOS 3846/* 39-47 */47#define RESET_ETH 4848/* 49-51 */49#define RESET_DEMOD 5250/* 53-63 */51 52/* RESET2 */53#define RESET_ABUS_ARB 6454#define RESET_IR_CTRL 6555#define RESET_TEMPSENSOR_DDR 6656#define RESET_TEMPSENSOR_PLL 6757/* 68-71 */58#define RESET_SMART_CARD 7259#define RESET_SPICC0 7360/* 74 */61#define RESET_RSA 7562/* 76-79 */63#define RESET_MSR_CLK 8064#define RESET_SPIFC 8165#define RESET_SARADC 8266/* 83-87 */67#define RESET_ACODEC 8868#define RESET_CEC 8969#define RESET_AFIFO 9070#define RESET_WATCHDOG 9171/* 92-95 */72 73/* RESET3 */74/* 96-127 */75 76/* RESET4 */77/* 128-131 */78#define RESET_PWM_AB 13279#define RESET_PWM_CD 13380#define RESET_PWM_EF 13481#define RESET_PWM_GH 13582#define RESET_PWM_IJ 13683/* 137 */84#define RESET_UART_A 13885#define RESET_UART_B 13986#define RESET_UART_C 14087#define RESET_UART_D 14188#define RESET_UART_E 14289/* 143 */90#define RESET_I2C_S_A 14491#define RESET_I2C_M_A 14592#define RESET_I2C_M_B 14693#define RESET_I2C_M_C 14794#define RESET_I2C_M_D 14895#define RESET_I2C_M_E 14996/* 150-151 */97#define RESET_SD_EMMC_A 15298#define RESET_SD_EMMC_B 15399#define RESET_NAND_EMMC 154100/* 155-159 */101 102/* RESET5 */103#define RESET_BRG_VDEC_PIPL0 160104#define RESET_BRG_HEVCF_PIPL0 161105/* 162 */106#define RESET_BRG_HCODEC_PIPL0 163107#define RESET_BRG_GE2D_PIPL0 164108#define RESET_BRG_VPU_PIPL0 165109#define RESET_BRG_CPU_PIPL0 166110#define RESET_BRG_MALI_PIPL0 167111/* 168 */112#define RESET_BRG_MALI_PIPL1 169113/* 170-171 */114#define RESET_BRG_HEVCF_PIPL1 172115#define RESET_BRG_HEVCB_PIPL1 173116/* 174-183 */117#define RESET_RAMA 184118/* 185-186 */119#define RESET_BRG_NIC_VAPB 187120#define RESET_BRG_NIC_DSU 188121#define RESET_BRG_NIC_SYSCLK 189122#define RESET_BRG_NIC_MAIN 190123#define RESET_BRG_NIC_ALL 191124 125#endif126