127 lines · c
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */2/*3 * Copyright (c) 2016 BayLibre, SAS.4 * Author: Neil Armstrong <narmstrong@baylibre.com>5 */6#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H7#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H8 9/* RESET0 */10#define RESET_HIU 011#define RESET_VLD 112#define RESET_IQIDCT 213#define RESET_MC 314/* 8 */15#define RESET_VIU 516#define RESET_AIU 617#define RESET_MCPU 718#define RESET_CCPU 819#define RESET_PMUX 920#define RESET_VENC 1021#define RESET_ASSIST 1122#define RESET_AFIFO2 1223#define RESET_MDEC 1324#define RESET_VLD_PART 1425#define RESET_VIFIFO 1526/* 16-31 */27/* RESET1 */28/* 32 */29#define RESET_DEMUX 3330#define RESET_USB_OTG 3431#define RESET_DDR 3532#define RESET_VDAC_1 3633#define RESET_BT656 3734#define RESET_AHB_SRAM 3835#define RESET_AHB_BRIDGE 3936#define RESET_PARSER 4037#define RESET_BLKMV 4138#define RESET_ISA 4239#define RESET_ETHERNET 4340#define RESET_ABUF 4441#define RESET_AHB_DATA 4542#define RESET_AHB_CNTL 4643#define RESET_ROM_BOOT 4744/* 48-63 */45/* RESET2 */46#define RESET_VD_RMEM 6447#define RESET_AUDIN 6548#define RESET_DBLK 6649#define RESET_PIC_DC 6750#define RESET_PSC 6851#define RESET_NAND 6952#define RESET_GE2D 7053#define RESET_PARSER_REG 7154#define RESET_PARSER_FETCH 7255#define RESET_PARSER_CTL 7356#define RESET_PARSER_TOP 7457#define RESET_HDMI_APB 7558#define RESET_AUDIO_APB 7659#define RESET_MEDIA_CPU 7760#define RESET_MALI 7861#define RESET_HDMI_SYSTEM_RESET 7962/* 80-95 */63/* RESET3 */64#define RESET_RING_OSCILLATOR 9665#define RESET_SYS_CPU_0 9766#define RESET_EFUSE 9867#define RESET_SYS_CPU_BVCI 9968#define RESET_AIFIFO 10069#define RESET_AUDIO_PLL_MODULATOR 10170#define RESET_AHB_BRIDGE_CNTL 10271#define RESET_SYS_CPU_1 10372#define RESET_AUDIO_DAC 10473#define RESET_DEMUX_TOP 10574#define RESET_DEMUX_DES 10675#define RESET_DEMUX_S2P_0 10776#define RESET_DEMUX_S2P_1 10877#define RESET_DEMUX_RESET_0 10978#define RESET_DEMUX_RESET_1 11079#define RESET_DEMUX_RESET_2 11180/* 112-127 */81/* RESET4 */82#define RESET_PL310 12883#define RESET_A5_APB 12984#define RESET_A5_AXI 13085#define RESET_A5 13186#define RESET_DVIN 13287#define RESET_RDMA 13388#define RESET_VENCI 13489#define RESET_VENCP 13590#define RESET_VENCT 13691#define RESET_VDAC_4 13792#define RESET_RTC 13893#define RESET_A5_DEBUG 13994#define RESET_VDI6 14095#define RESET_VENCL 14196/* 142-159 */97/* RESET5 */98#define RESET_DDR_PLL 16099#define RESET_MISC_PLL 161100#define RESET_SYS_PLL 162101#define RESET_HPLL_PLL 163102#define RESET_AUDIO_PLL 164103#define RESET_VID2_PLL 165104/* 166-191 */105/* RESET6 */106#define RESET_PERIPHS_GENERAL 192107#define RESET_PERIPHS_IR_REMOTE 193108#define RESET_PERIPHS_SMART_CARD 194109#define RESET_PERIPHS_SAR_ADC 195110#define RESET_PERIPHS_I2C_MASTER_0 196111#define RESET_PERIPHS_I2C_MASTER_1 197112#define RESET_PERIPHS_I2C_SLAVE 198113#define RESET_PERIPHS_STREAM_INTERFACE 199114#define RESET_PERIPHS_SDIO 200115#define RESET_PERIPHS_UART_0 201116#define RESET_PERIPHS_UART_1 202117#define RESET_PERIPHS_ASYNC_0 203118#define RESET_PERIPHS_ASYNC_1 204119#define RESET_PERIPHS_SPI_0 205120#define RESET_PERIPHS_SPI_1 206121#define RESET_PERIPHS_LED_PWM 207122/* 208-223 */123/* RESET7 */124/* 224-255 */125 126#endif127