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1/* SPDX-License-Identifier: GPL-2.0 */2/**3 * This header provides index for the reset controller4 * based on hi6220 SoC.5 */6#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI62207#define _DT_BINDINGS_RESET_CONTROLLER_HI62208 9#define PERIPH_RSTDIS0_MMC0 0x00010#define PERIPH_RSTDIS0_MMC1 0x00111#define PERIPH_RSTDIS0_MMC2 0x00212#define PERIPH_RSTDIS0_NANDC 0x00313#define PERIPH_RSTDIS0_USBOTG_BUS 0x00414#define PERIPH_RSTDIS0_POR_PICOPHY 0x00515#define PERIPH_RSTDIS0_USBOTG 0x00616#define PERIPH_RSTDIS0_USBOTG_32K 0x00717#define PERIPH_RSTDIS1_HIFI 0x10018#define PERIPH_RSTDIS1_DIGACODEC 0x10519#define PERIPH_RSTEN2_IPF 0x20020#define PERIPH_RSTEN2_SOCP 0x20121#define PERIPH_RSTEN2_DMAC 0x20222#define PERIPH_RSTEN2_SECENG 0x20323#define PERIPH_RSTEN2_ABB 0x20424#define PERIPH_RSTEN2_HPM0 0x20525#define PERIPH_RSTEN2_HPM1 0x20626#define PERIPH_RSTEN2_HPM2 0x20727#define PERIPH_RSTEN2_HPM3 0x20828#define PERIPH_RSTEN3_CSSYS 0x30029#define PERIPH_RSTEN3_I2C0 0x30130#define PERIPH_RSTEN3_I2C1 0x30231#define PERIPH_RSTEN3_I2C2 0x30332#define PERIPH_RSTEN3_I2C3 0x30433#define PERIPH_RSTEN3_UART1 0x30534#define PERIPH_RSTEN3_UART2 0x30635#define PERIPH_RSTEN3_UART3 0x30736#define PERIPH_RSTEN3_UART4 0x30837#define PERIPH_RSTEN3_SSP 0x30938#define PERIPH_RSTEN3_PWM 0x30a39#define PERIPH_RSTEN3_BLPWM 0x30b40#define PERIPH_RSTEN3_TSENSOR 0x30c41#define PERIPH_RSTEN3_DAPB 0x31242#define PERIPH_RSTEN3_HKADC 0x31343#define PERIPH_RSTEN3_CODEC_SSI 0x31444#define PERIPH_RSTEN3_PMUSSI1 0x31645#define PERIPH_RSTEN8_RS0 0x40046#define PERIPH_RSTEN8_RS2 0x40147#define PERIPH_RSTEN8_RS3 0x40248#define PERIPH_RSTEN8_MS0 0x40349#define PERIPH_RSTEN8_MS2 0x40550#define PERIPH_RSTEN8_XG2RAM0 0x40651#define PERIPH_RSTEN8_X2SRAM_TZMA 0x40752#define PERIPH_RSTEN8_SRAM 0x40853#define PERIPH_RSTEN8_HARQ 0x40a54#define PERIPH_RSTEN8_DDRC 0x40c55#define PERIPH_RSTEN8_DDRC_APB 0x40d56#define PERIPH_RSTEN8_DDRPACK_APB 0x40e57#define PERIPH_RSTEN8_DDRT 0x41158#define PERIPH_RSDIST9_CARM_DAP 0x50059#define PERIPH_RSDIST9_CARM_ATB 0x50160#define PERIPH_RSDIST9_CARM_LBUS 0x50261#define PERIPH_RSDIST9_CARM_POR 0x50362#define PERIPH_RSDIST9_CARM_CORE 0x50463#define PERIPH_RSDIST9_CARM_DBG 0x50564#define PERIPH_RSDIST9_CARM_L2 0x50665#define PERIPH_RSDIST9_CARM_SOCDBG 0x50766#define PERIPH_RSDIST9_CARM_ETM 0x50867 68#define MEDIA_G3D 069#define MEDIA_CODEC_VPU 270#define MEDIA_CODEC_JPEG 371#define MEDIA_ISP 472#define MEDIA_ADE 573#define MEDIA_MMU 674#define MEDIA_XG2RAM1 775 76#define AO_G3D 177#define AO_CODECISP 278#define AO_MCPU 479#define AO_BBPHARQMEM 580#define AO_HIFI 881#define AO_ACPUSCUL2C 1282 83#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/84