43 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>4 * Copyright (c) 2020 Western Digital Corporation or its affiliates.5 */6#ifndef RESET_K210_SYSCTL_H7#define RESET_K210_SYSCTL_H8 9/*10 * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits.11 * Taken from Kendryte SDK (kendryte-standalone-sdk).12 */13#define K210_RST_ROM 014#define K210_RST_DMA 115#define K210_RST_AI 216#define K210_RST_DVP 317#define K210_RST_FFT 418#define K210_RST_GPIO 519#define K210_RST_SPI0 620#define K210_RST_SPI1 721#define K210_RST_SPI2 822#define K210_RST_SPI3 923#define K210_RST_I2S0 1024#define K210_RST_I2S1 1125#define K210_RST_I2S2 1226#define K210_RST_I2C0 1327#define K210_RST_I2C1 1428#define K210_RST_I2C2 1529#define K210_RST_UART1 1630#define K210_RST_UART2 1731#define K210_RST_UART3 1832#define K210_RST_AES 1933#define K210_RST_FPIOA 2034#define K210_RST_TIMER0 2135#define K210_RST_TIMER1 2236#define K210_RST_TIMER2 2337#define K210_RST_WDT0 2438#define K210_RST_WDT1 2539#define K210_RST_SHA 2640#define K210_RST_RTC 2941 42#endif /* RESET_K210_SYSCTL_H */43