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1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */2/*3 * Copyright (c) 2022 Collabora Ltd.4 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>5 */6 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT67958#define _DT_BINDINGS_RESET_CONTROLLER_MT67959 10/* INFRACFG resets */11#define MT6795_INFRA_RST0_SCPSYS_RST 012#define MT6795_INFRA_RST0_PMIC_WRAP_RST 113#define MT6795_INFRA_RST1_MIPI_DSI_RST 214#define MT6795_INFRA_RST1_MIPI_CSI_RST 315#define MT6795_INFRA_RST1_MM_IOMMU_RST 416 17/* MMSYS resets */18#define MT6795_MMSYS_SW0_RST_B_SMI_COMMON 019#define MT6795_MMSYS_SW0_RST_B_SMI_LARB 120#define MT6795_MMSYS_SW0_RST_B_CAM_MDP 221#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA0 322#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA1 423#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ0 524#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ1 625#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ2 726#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP0 827#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP1 928#define MT6795_MMSYS_SW0_RST_B_MDP_WDMA 1029#define MT6795_MMSYS_SW0_RST_B_MDP_WROT0 1130#define MT6795_MMSYS_SW0_RST_B_MDP_WROT1 1231#define MT6795_MMSYS_SW0_RST_B_MDP_CROP 1332 33/* PERICFG resets */34#define MT6795_PERI_NFI_SW_RST 035#define MT6795_PERI_THERM_SW_RST 136#define MT6795_PERI_MSDC1_SW_RST 237 38/* TOPRGU resets */39#define MT6795_TOPRGU_INFRA_SW_RST 040#define MT6795_TOPRGU_MM_SW_RST 141#define MT6795_TOPRGU_MFG_SW_RST 242#define MT6795_TOPRGU_VENC_SW_RST 343#define MT6795_TOPRGU_VDEC_SW_RST 444#define MT6795_TOPRGU_IMG_SW_RST 545#define MT6795_TOPRGU_DDRPHY_SW_RST 646#define MT6795_TOPRGU_MD_SW_RST 747#define MT6795_TOPRGU_INFRA_AO_SW_RST 848#define MT6795_TOPRGU_MD_LITE_SW_RST 949#define MT6795_TOPRGU_APMIXED_SW_RST 1050#define MT6795_TOPRGU_PWRAP_SPI_CTL_RST 1151#define MT6795_TOPRGU_SW_RST_NUM 1252 53#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6795 */54