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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com>4 */5 6#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT27017#define _DT_BINDINGS_RESET_CONTROLLER_MT27018 9/* INFRACFG resets */10#define MT2701_INFRA_EMI_REG_RST 011#define MT2701_INFRA_DRAMC0_A0_RST 112#define MT2701_INFRA_FHCTL_RST 213#define MT2701_INFRA_APCIRQ_EINT_RST 314#define MT2701_INFRA_APXGPT_RST 415#define MT2701_INFRA_SCPSYS_RST 516#define MT2701_INFRA_KP_RST 617#define MT2701_INFRA_PMIC_WRAP_RST 718#define MT2701_INFRA_MIPI_RST 819#define MT2701_INFRA_IRRX_RST 920#define MT2701_INFRA_CEC_RST 1021#define MT2701_INFRA_EMI_RST 3222#define MT2701_INFRA_DRAMC0_RST 3423#define MT2701_INFRA_TRNG_RST 3724#define MT2701_INFRA_SYSIRQ_RST 3825 26/* PERICFG resets */27#define MT2701_PERI_UART0_SW_RST 028#define MT2701_PERI_UART1_SW_RST 129#define MT2701_PERI_UART2_SW_RST 230#define MT2701_PERI_UART3_SW_RST 331#define MT2701_PERI_GCPU_SW_RST 532#define MT2701_PERI_BTIF_SW_RST 633#define MT2701_PERI_PWM_SW_RST 834#define MT2701_PERI_AUXADC_SW_RST 1035#define MT2701_PERI_DMA_SW_RST 1136#define MT2701_PERI_NFI_SW_RST 1437#define MT2701_PERI_NLI_SW_RST 1538#define MT2701_PERI_THERM_SW_RST 1639#define MT2701_PERI_MSDC2_SW_RST 1740#define MT2701_PERI_MSDC0_SW_RST 1941#define MT2701_PERI_MSDC1_SW_RST 2042#define MT2701_PERI_I2C0_SW_RST 2243#define MT2701_PERI_I2C1_SW_RST 2344#define MT2701_PERI_I2C2_SW_RST 2445#define MT2701_PERI_I2C3_SW_RST 2546#define MT2701_PERI_USB_SW_RST 2847#define MT2701_PERI_ETH_SW_RST 2948#define MT2701_PERI_SPI0_SW_RST 3349 50/* TOPRGU resets */51#define MT2701_TOPRGU_INFRA_RST 052#define MT2701_TOPRGU_MM_RST 153#define MT2701_TOPRGU_MFG_RST 254#define MT2701_TOPRGU_ETHDMA_RST 355#define MT2701_TOPRGU_VDEC_RST 456#define MT2701_TOPRGU_VENC_IMG_RST 557#define MT2701_TOPRGU_DDRPHY_RST 658#define MT2701_TOPRGU_MD_RST 759#define MT2701_TOPRGU_INFRA_AO_RST 860#define MT2701_TOPRGU_CONN_RST 961#define MT2701_TOPRGU_APMIXED_RST 1062#define MT2701_TOPRGU_HIFSYS_RST 1163#define MT2701_TOPRGU_CONN_MCU_RST 1264#define MT2701_TOPRGU_BDP_DISP_RST 1365 66/* HIFSYS resets */67#define MT2701_HIFSYS_UHOST0_RST 368#define MT2701_HIFSYS_UHOST1_RST 469#define MT2701_HIFSYS_UPHY0_RST 2170#define MT2701_HIFSYS_UPHY1_RST 2271#define MT2701_HIFSYS_PCIE0_RST 2472#define MT2701_HIFSYS_PCIE1_RST 2573#define MT2701_HIFSYS_PCIE2_RST 2674 75/* ETHSYS resets */76#define MT2701_ETHSYS_SYS_RST 077#define MT2701_ETHSYS_MCM_RST 278#define MT2701_ETHSYS_FE_RST 679#define MT2701_ETHSYS_GMAC_RST 2380#define MT2701_ETHSYS_PPE_RST 3181 82/* G3DSYS resets */83#define MT2701_G3DSYS_CORE_RST 084 85#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */86