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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2017 MediaTek Inc.4 * Author: Sean Wang <sean.wang@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT76228#define _DT_BINDINGS_RESET_CONTROLLER_MT76229 10/* INFRACFG resets */11#define MT7622_INFRA_EMI_REG_RST 012#define MT7622_INFRA_DRAMC0_A0_RST 113#define MT7622_INFRA_APCIRQ_EINT_RST 314#define MT7622_INFRA_APXGPT_RST 415#define MT7622_INFRA_SCPSYS_RST 516#define MT7622_INFRA_PMIC_WRAP_RST 717#define MT7622_INFRA_IRRX_RST 918#define MT7622_INFRA_EMI_RST 1619#define MT7622_INFRA_WED0_RST 1720#define MT7622_INFRA_DRAMC_RST 1821#define MT7622_INFRA_CCI_INTF_RST 1922#define MT7622_INFRA_TRNG_RST 2123#define MT7622_INFRA_SYSIRQ_RST 2224#define MT7622_INFRA_WED1_RST 2525 26/* PERICFG Subsystem resets */27#define MT7622_PERI_UART0_SW_RST 028#define MT7622_PERI_UART1_SW_RST 129#define MT7622_PERI_UART2_SW_RST 230#define MT7622_PERI_UART3_SW_RST 331#define MT7622_PERI_UART4_SW_RST 432#define MT7622_PERI_BTIF_SW_RST 633#define MT7622_PERI_PWM_SW_RST 834#define MT7622_PERI_AUXADC_SW_RST 1035#define MT7622_PERI_DMA_SW_RST 1136#define MT7622_PERI_IRTX_SW_RST 1337#define MT7622_PERI_NFI_SW_RST 1438#define MT7622_PERI_THERM_SW_RST 1639#define MT7622_PERI_MSDC0_SW_RST 1940#define MT7622_PERI_MSDC1_SW_RST 2041#define MT7622_PERI_I2C0_SW_RST 2242#define MT7622_PERI_I2C1_SW_RST 2343#define MT7622_PERI_I2C2_SW_RST 2444#define MT7622_PERI_SPI0_SW_RST 3345#define MT7622_PERI_SPI1_SW_RST 3446#define MT7622_PERI_FLASHIF_SW_RST 3647 48/* TOPRGU resets */49#define MT7622_TOPRGU_INFRA_RST 050#define MT7622_TOPRGU_ETHDMA_RST 151#define MT7622_TOPRGU_DDRPHY_RST 652#define MT7622_TOPRGU_INFRA_AO_RST 853#define MT7622_TOPRGU_CONN_RST 954#define MT7622_TOPRGU_APMIXED_RST 1055#define MT7622_TOPRGU_CONN_MCU_RST 1256 57/* PCIe/SATA Subsystem resets */58#define MT7622_SATA_PHY_REG_RST 1259#define MT7622_SATA_PHY_SW_RST 1360#define MT7622_SATA_AXI_BUS_RST 1561#define MT7622_PCIE1_CORE_RST 1962#define MT7622_PCIE1_MMIO_RST 2063#define MT7622_PCIE1_HRST 2164#define MT7622_PCIE1_USER_RST 2265#define MT7622_PCIE1_PIPE_RST 2366#define MT7622_PCIE0_CORE_RST 2767#define MT7622_PCIE0_MMIO_RST 2868#define MT7622_PCIE0_HRST 2969#define MT7622_PCIE0_USER_RST 3070#define MT7622_PCIE0_PIPE_RST 3171 72/* SSUSB Subsystem resets */73#define MT7622_SSUSB_PHY_PWR_RST 374#define MT7622_SSUSB_MAC_PWR_RST 475 76/* ETHSYS Subsystem resets */77#define MT7622_ETHSYS_SYS_RST 078#define MT7622_ETHSYS_MCM_RST 279#define MT7622_ETHSYS_HSDMA_RST 580#define MT7622_ETHSYS_FE_RST 681#define MT7622_ETHSYS_GMAC_RST 2382#define MT7622_ETHSYS_EPHY_RST 2483#define MT7622_ETHSYS_CRYPTO_RST 2984#define MT7622_ETHSYS_PPE_RST 3185 86#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */87