72 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (C) 2019 MediaTek Inc.4 */5 6#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT76297#define _DT_BINDINGS_RESET_CONTROLLER_MT76298 9/* INFRACFG resets */10#define MT7629_INFRA_EMI_MPU_RST 011#define MT7629_INFRA_UART5_RST 212#define MT7629_INFRA_CIRQ_EINT_RST 313#define MT7629_INFRA_APXGPT_RST 414#define MT7629_INFRA_SCPSYS_RST 515#define MT7629_INFRA_KP_RST 616#define MT7629_INFRA_SPI1_RST 717#define MT7629_INFRA_SPI4_RST 818#define MT7629_INFRA_SYSTIMER_RST 919#define MT7629_INFRA_IRRX_RST 1020#define MT7629_INFRA_AO_BUS_RST 1621#define MT7629_INFRA_EMI_RST 3222#define MT7629_INFRA_APMIXED_RST 3523#define MT7629_INFRA_MIPI_RST 3624#define MT7629_INFRA_TRNG_RST 3725#define MT7629_INFRA_SYSCIRQ_RST 3826#define MT7629_INFRA_MIPI_CSI_RST 3927#define MT7629_INFRA_GCE_FAXI_RST 4028#define MT7629_INFRA_I2C_SRAM_RST 4129#define MT7629_INFRA_IOMMU_RST 4730 31/* PERICFG resets */32#define MT7629_PERI_UART0_SW_RST 033#define MT7629_PERI_UART1_SW_RST 134#define MT7629_PERI_UART2_SW_RST 235#define MT7629_PERI_BTIF_SW_RST 636#define MT7629_PERI_PWN_SW_RST 837#define MT7629_PERI_DMA_SW_RST 1138#define MT7629_PERI_NFI_SW_RST 1439#define MT7629_PERI_I2C0_SW_RST 2240#define MT7629_PERI_SPI0_SW_RST 3341#define MT7629_PERI_SPI1_SW_RST 3442#define MT7629_PERI_FLASHIF_SW_RST 3643 44/* PCIe Subsystem resets */45#define MT7629_PCIE1_CORE_RST 1946#define MT7629_PCIE1_MMIO_RST 2047#define MT7629_PCIE1_HRST 2148#define MT7629_PCIE1_USER_RST 2249#define MT7629_PCIE1_PIPE_RST 2350#define MT7629_PCIE0_CORE_RST 2751#define MT7629_PCIE0_MMIO_RST 2852#define MT7629_PCIE0_HRST 2953#define MT7629_PCIE0_USER_RST 3054#define MT7629_PCIE0_PIPE_RST 3155 56/* SSUSB Subsystem resets */57#define MT7629_SSUSB_PHY_PWR_RST 358#define MT7629_SSUSB_MAC_PWR_RST 459 60/* ETH Subsystem resets */61#define MT7629_ETHSYS_SYS_RST 062#define MT7629_ETHSYS_MCM_RST 263#define MT7629_ETHSYS_HSDMA_RST 564#define MT7629_ETHSYS_FE_RST 665#define MT7629_ETHSYS_ESW_RST 1666#define MT7629_ETHSYS_GMAC_RST 2367#define MT7629_ETHSYS_EPHY_RST 2468#define MT7629_ETHSYS_CRYPTO_RST 2969#define MT7629_ETHSYS_PPE_RST 3170 71#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */72