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1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Sam Shih <sam.shih@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT79868#define _DT_BINDINGS_RESET_CONTROLLER_MT79869 10/* INFRACFG resets */11#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 612#define MT7986_INFRACFG_SSUSB_SW_RST 713#define MT7986_INFRACFG_EIP97_SW_RST 814#define MT7986_INFRACFG_AUDIO_SW_RST 1315#define MT7986_INFRACFG_CQ_DMA_SW_RST 1416 17#define MT7986_INFRACFG_TRNG_SW_RST 1718#define MT7986_INFRACFG_AP_DMA_SW_RST 3219#define MT7986_INFRACFG_I2C_SW_RST 3320#define MT7986_INFRACFG_NFI_SW_RST 3421#define MT7986_INFRACFG_SPI0_SW_RST 3522#define MT7986_INFRACFG_SPI1_SW_RST 3623#define MT7986_INFRACFG_UART0_SW_RST 3724#define MT7986_INFRACFG_UART1_SW_RST 3825#define MT7986_INFRACFG_UART2_SW_RST 3926#define MT7986_INFRACFG_AUXADC_SW_RST 4327 28#define MT7986_INFRACFG_APXGPT_SW_RST 6629#define MT7986_INFRACFG_PWM_SW_RST 6830 31#define MT7986_INFRACFG_SW_RST_NUM 6932 33/* TOPRGU resets */34#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 035#define MT7986_TOPRGU_SGMII0_SW_RST 136#define MT7986_TOPRGU_SGMII1_SW_RST 237#define MT7986_TOPRGU_INFRA_SW_RST 338#define MT7986_TOPRGU_U2PHY_SW_RST 539#define MT7986_TOPRGU_PCIE_SW_RST 640#define MT7986_TOPRGU_SSUSB_SW_RST 741#define MT7986_TOPRGU_ETHDMA_SW_RST 2042#define MT7986_TOPRGU_CONSYS_SW_RST 2343 44#define MT7986_TOPRGU_SW_RST_NUM 2445 46/* ETHSYS Subsystem resets */47#define MT7986_ETHSYS_FE_SW_RST 648#define MT7986_ETHSYS_PMTR_SW_RST 849#define MT7986_ETHSYS_GMAC_SW_RST 2350#define MT7986_ETHSYS_PPE0_SW_RST 3051#define MT7986_ETHSYS_PPE1_SW_RST 3152 53#define MT7986_ETHSYS_SW_RST_NUM 3254 55#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */56