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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Author: Flora Fu, MediaTek5 */6 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT81358#define _DT_BINDINGS_RESET_CONTROLLER_MT81359 10/* INFRACFG resets */11#define MT8135_INFRA_EMI_REG_RST 012#define MT8135_INFRA_DRAMC0_A0_RST 113#define MT8135_INFRA_CCIF0_RST 214#define MT8135_INFRA_APCIRQ_EINT_RST 315#define MT8135_INFRA_APXGPT_RST 416#define MT8135_INFRA_SCPSYS_RST 517#define MT8135_INFRA_CCIF1_RST 618#define MT8135_INFRA_PMIC_WRAP_RST 719#define MT8135_INFRA_KP_RST 820#define MT8135_INFRA_EMI_RST 3221#define MT8135_INFRA_DRAMC0_RST 3422#define MT8135_INFRA_SMI_RST 3523#define MT8135_INFRA_M4U_RST 3624 25/* PERICFG resets */26#define MT8135_PERI_UART0_SW_RST 027#define MT8135_PERI_UART1_SW_RST 128#define MT8135_PERI_UART2_SW_RST 229#define MT8135_PERI_UART3_SW_RST 330#define MT8135_PERI_IRDA_SW_RST 431#define MT8135_PERI_PTP_SW_RST 532#define MT8135_PERI_AP_HIF_SW_RST 633#define MT8135_PERI_GPCU_SW_RST 734#define MT8135_PERI_MD_HIF_SW_RST 835#define MT8135_PERI_NLI_SW_RST 936#define MT8135_PERI_AUXADC_SW_RST 1037#define MT8135_PERI_DMA_SW_RST 1138#define MT8135_PERI_NFI_SW_RST 1439#define MT8135_PERI_PWM_SW_RST 1540#define MT8135_PERI_THERM_SW_RST 1641#define MT8135_PERI_MSDC0_SW_RST 1742#define MT8135_PERI_MSDC1_SW_RST 1843#define MT8135_PERI_MSDC2_SW_RST 1944#define MT8135_PERI_MSDC3_SW_RST 2045#define MT8135_PERI_I2C0_SW_RST 2246#define MT8135_PERI_I2C1_SW_RST 2347#define MT8135_PERI_I2C2_SW_RST 2448#define MT8135_PERI_I2C3_SW_RST 2549#define MT8135_PERI_I2C4_SW_RST 2650#define MT8135_PERI_I2C5_SW_RST 2751#define MT8135_PERI_I2C6_SW_RST 2852#define MT8135_PERI_USB_SW_RST 2953#define MT8135_PERI_SPI1_SW_RST 3354#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 3455 56#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */57