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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Author: Flora Fu, MediaTek5 */6 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT81738#define _DT_BINDINGS_RESET_CONTROLLER_MT81739 10/* INFRACFG resets */11#define MT8173_INFRA_EMI_REG_RST 012#define MT8173_INFRA_DRAMC0_A0_RST 113#define MT8173_INFRA_APCIRQ_EINT_RST 314#define MT8173_INFRA_APXGPT_RST 415#define MT8173_INFRA_SCPSYS_RST 516#define MT8173_INFRA_KP_RST 617#define MT8173_INFRA_PMIC_WRAP_RST 718#define MT8173_INFRA_MPIP_RST 819#define MT8173_INFRA_CEC_RST 920#define MT8173_INFRA_EMI_RST 3221#define MT8173_INFRA_DRAMC0_RST 3422#define MT8173_INFRA_APMIXEDSYS_RST 3523#define MT8173_INFRA_MIPI_DSI_RST 3624#define MT8173_INFRA_TRNG_RST 3725#define MT8173_INFRA_SYSIRQ_RST 3826#define MT8173_INFRA_MIPI_CSI_RST 3927#define MT8173_INFRA_GCE_FAXI_RST 4028#define MT8173_INFRA_MMIOMMURST 4729 30/* MMSYS resets */31#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 2532 33/* PERICFG resets */34#define MT8173_PERI_UART0_SW_RST 035#define MT8173_PERI_UART1_SW_RST 136#define MT8173_PERI_UART2_SW_RST 237#define MT8173_PERI_UART3_SW_RST 338#define MT8173_PERI_IRRX_SW_RST 439#define MT8173_PERI_PWM_SW_RST 840#define MT8173_PERI_AUXADC_SW_RST 1041#define MT8173_PERI_DMA_SW_RST 1142#define MT8173_PERI_I2C6_SW_RST 1343#define MT8173_PERI_NFI_SW_RST 1444#define MT8173_PERI_THERM_SW_RST 1645#define MT8173_PERI_MSDC2_SW_RST 1746#define MT8173_PERI_MSDC3_SW_RST 1847#define MT8173_PERI_MSDC0_SW_RST 1948#define MT8173_PERI_MSDC1_SW_RST 2049#define MT8173_PERI_I2C0_SW_RST 2250#define MT8173_PERI_I2C1_SW_RST 2351#define MT8173_PERI_I2C2_SW_RST 2452#define MT8173_PERI_I2C3_SW_RST 2553#define MT8173_PERI_I2C4_SW_RST 2654#define MT8173_PERI_HDMI_SW_RST 2955#define MT8173_PERI_SPI0_SW_RST 3356 57#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */58