42 lines · c
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Runyang Chen <runyang.chen@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT81868#define _DT_BINDINGS_RESET_CONTROLLER_MT81869 10/* TOPRGU resets */11#define MT8186_TOPRGU_INFRA_SW_RST 012#define MT8186_TOPRGU_MM_SW_RST 113#define MT8186_TOPRGU_MFG_SW_RST 214#define MT8186_TOPRGU_VENC_SW_RST 315#define MT8186_TOPRGU_VDEC_SW_RST 416#define MT8186_TOPRGU_IMG_SW_RST 517#define MT8186_TOPRGU_DDR_SW_RST 618#define MT8186_TOPRGU_INFRA_AO_SW_RST 819#define MT8186_TOPRGU_CONNSYS_SW_RST 920#define MT8186_TOPRGU_APMIXED_SW_RST 1021#define MT8186_TOPRGU_PWRAP_SW_RST 1122#define MT8186_TOPRGU_CONN_MCU_SW_RST 1223#define MT8186_TOPRGU_IPNNA_SW_RST 1324#define MT8186_TOPRGU_WPE_SW_RST 1425#define MT8186_TOPRGU_ADSP_SW_RST 1526#define MT8186_TOPRGU_AUDIO_SW_RST 1727#define MT8186_TOPRGU_CAM_MAIN_SW_RST 1828#define MT8186_TOPRGU_CAM_RAWA_SW_RST 1929#define MT8186_TOPRGU_CAM_RAWB_SW_RST 2030#define MT8186_TOPRGU_IPE_SW_RST 2131#define MT8186_TOPRGU_IMG2_SW_RST 2232#define MT8186_TOPRGU_SW_RST_NUM 2333 34/* MMSYS resets */35#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 1936 37/* INFRA resets */38#define MT8186_INFRA_THERMAL_CTRL_RST 039#define MT8186_INFRA_PTP_CTRL_RST 140 41#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */42