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1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Runyang Chen <runyang.chen@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT81888#define _DT_BINDINGS_RESET_CONTROLLER_MT81889 10#define MT8188_TOPRGU_CONN_MCU_SW_RST 011#define MT8188_TOPRGU_INFRA_GRST_SW_RST 112#define MT8188_TOPRGU_IPU0_SW_RST 213#define MT8188_TOPRGU_IPU1_SW_RST 314#define MT8188_TOPRGU_IPU2_SW_RST 415#define MT8188_TOPRGU_AUD_ASRC_SW_RST 516#define MT8188_TOPRGU_INFRA_SW_RST 617#define MT8188_TOPRGU_MMSYS_SW_RST 718#define MT8188_TOPRGU_MFG_SW_RST 819#define MT8188_TOPRGU_VENC_SW_RST 920#define MT8188_TOPRGU_VDEC_SW_RST 1021#define MT8188_TOPRGU_CAM_VCORE_SW_RST 1122#define MT8188_TOPRGU_SCP_SW_RST 1223#define MT8188_TOPRGU_APMIXEDSYS_SW_RST 1324#define MT8188_TOPRGU_AUDIO_SW_RST 1425#define MT8188_TOPRGU_CAMSYS_SW_RST 1526#define MT8188_TOPRGU_MJC_SW_RST 1627#define MT8188_TOPRGU_PERI_SW_RST 1728#define MT8188_TOPRGU_PERI_AO_SW_RST 1829#define MT8188_TOPRGU_PCIE_SW_RST 1930#define MT8188_TOPRGU_ADSPSYS_SW_RST 2131#define MT8188_TOPRGU_DPTX_SW_RST 2232#define MT8188_TOPRGU_SPMI_MST_SW_RST 2333 34#define MT8188_TOPRGU_SW_RST_NUM 2435 36/* INFRA resets */37#define MT8188_INFRA_RST1_THERMAL_MCU_RST 038#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 139#define MT8188_INFRA_RST3_PTP_CTRL_RST 240 41#define MT8188_VDO0_RST_DISP_OVL0 042#define MT8188_VDO0_RST_FAKE_ENG0 143#define MT8188_VDO0_RST_DISP_CCORR0 244#define MT8188_VDO0_RST_DISP_MUTEX0 345#define MT8188_VDO0_RST_DISP_GAMMA0 446#define MT8188_VDO0_RST_DISP_DITHER0 547#define MT8188_VDO0_RST_DISP_WDMA0 648#define MT8188_VDO0_RST_DISP_RDMA0 749#define MT8188_VDO0_RST_DSI0 850#define MT8188_VDO0_RST_DSI1 951#define MT8188_VDO0_RST_DSC_WRAP0 1052#define MT8188_VDO0_RST_VPP_MERGE0 1153#define MT8188_VDO0_RST_DP_INTF0 1254#define MT8188_VDO0_RST_DISP_AAL0 1355#define MT8188_VDO0_RST_INLINEROT0 1456#define MT8188_VDO0_RST_APB_BUS 1557#define MT8188_VDO0_RST_DISP_COLOR0 1658#define MT8188_VDO0_RST_MDP_WROT0 1759#define MT8188_VDO0_RST_DISP_RSZ0 1860 61#define MT8188_VDO1_RST_SMI_LARB2 062#define MT8188_VDO1_RST_SMI_LARB3 163#define MT8188_VDO1_RST_GALS 264#define MT8188_VDO1_RST_FAKE_ENG0 365#define MT8188_VDO1_RST_FAKE_ENG1 466#define MT8188_VDO1_RST_MDP_RDMA0 567#define MT8188_VDO1_RST_MDP_RDMA1 668#define MT8188_VDO1_RST_MDP_RDMA2 769#define MT8188_VDO1_RST_MDP_RDMA3 870#define MT8188_VDO1_RST_VPP_MERGE0 971#define MT8188_VDO1_RST_VPP_MERGE1 1072#define MT8188_VDO1_RST_VPP_MERGE2 1173#define MT8188_VDO1_RST_VPP_MERGE3 1274#define MT8188_VDO1_RST_VPP_MERGE4 1375#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 1476#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 1577#define MT8188_VDO1_RST_DISP_MUTEX 1678#define MT8188_VDO1_RST_MDP_RDMA4 1779#define MT8188_VDO1_RST_MDP_RDMA5 1880#define MT8188_VDO1_RST_MDP_RDMA6 1981#define MT8188_VDO1_RST_MDP_RDMA7 2082#define MT8188_VDO1_RST_DP_INTF1_MMCK 2183#define MT8188_VDO1_RST_DPI0_MM_CK 2284#define MT8188_VDO1_RST_DPI1_MM_CK 2385#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 2486#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 2587#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 2688#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 2789#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 2890#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 2991#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 3092#define MT8188_VDO1_RST_PADDING0 3193#define MT8188_VDO1_RST_PADDING1 3294#define MT8188_VDO1_RST_PADDING2 3395#define MT8188_VDO1_RST_PADDING3 3496#define MT8188_VDO1_RST_PADDING4 3597#define MT8188_VDO1_RST_PADDING5 3698#define MT8188_VDO1_RST_PADDING6 3799#define MT8188_VDO1_RST_PADDING7 38100#define MT8188_VDO1_RST_DISP_RSZ0 39101#define MT8188_VDO1_RST_DISP_RSZ1 40102#define MT8188_VDO1_RST_DISP_RSZ2 41103#define MT8188_VDO1_RST_DISP_RSZ3 42104#define MT8188_VDO1_RST_HDR_VDO_FE0 43105#define MT8188_VDO1_RST_HDR_GFX_FE0 44106#define MT8188_VDO1_RST_HDR_VDO_BE 45107#define MT8188_VDO1_RST_HDR_VDO_FE1 46108#define MT8188_VDO1_RST_HDR_GFX_FE1 47109#define MT8188_VDO1_RST_DISP_MIXER 48110#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49111#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50112#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51113#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52114#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53115 116#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */117