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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2020 MediaTek Inc.4 * Author: Yong Liang <yong.liang@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT81928#define _DT_BINDINGS_RESET_CONTROLLER_MT81929 10/* TOPRGU resets */11#define MT8192_TOPRGU_MM_SW_RST 112#define MT8192_TOPRGU_MFG_SW_RST 213#define MT8192_TOPRGU_VENC_SW_RST 314#define MT8192_TOPRGU_VDEC_SW_RST 415#define MT8192_TOPRGU_IMG_SW_RST 516#define MT8192_TOPRGU_MD_SW_RST 717#define MT8192_TOPRGU_CONN_SW_RST 918#define MT8192_TOPRGU_CONN_MCU_SW_RST 1219#define MT8192_TOPRGU_IPU0_SW_RST 1420#define MT8192_TOPRGU_IPU1_SW_RST 1521#define MT8192_TOPRGU_AUDIO_SW_RST 1722#define MT8192_TOPRGU_CAMSYS_SW_RST 1823#define MT8192_TOPRGU_MJC_SW_RST 1924#define MT8192_TOPRGU_C2K_S2_SW_RST 2025#define MT8192_TOPRGU_C2K_SW_RST 2126#define MT8192_TOPRGU_PERI_SW_RST 2227#define MT8192_TOPRGU_PERI_AO_SW_RST 2328 29#define MT8192_TOPRGU_SW_RST_NUM 2330 31/* MMSYS resets */32#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 1533 34/* INFRA resets */35#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 036#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 137#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 238#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 339#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 440 41#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */42