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1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/2/*3 * Copyright (c) 2021 MediaTek Inc.4 * Author: Christine Zhu <christine.zhu@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT81958#define _DT_BINDINGS_RESET_CONTROLLER_MT81959 10/* TOPRGU resets */11#define MT8195_TOPRGU_CONN_MCU_SW_RST 012#define MT8195_TOPRGU_INFRA_GRST_SW_RST 113#define MT8195_TOPRGU_APU_SW_RST 214#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 615#define MT8195_TOPRGU_MMSYS_SW_RST 716#define MT8195_TOPRGU_MFG_SW_RST 817#define MT8195_TOPRGU_VENC_SW_RST 918#define MT8195_TOPRGU_VDEC_SW_RST 1019#define MT8195_TOPRGU_IMG_SW_RST 1120#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 1321#define MT8195_TOPRGU_AUDIO_SW_RST 1422#define MT8195_TOPRGU_CAMSYS_SW_RST 1523#define MT8195_TOPRGU_EDPTX_SW_RST 1624#define MT8195_TOPRGU_ADSPSYS_SW_RST 2125#define MT8195_TOPRGU_DPTX_SW_RST 2226#define MT8195_TOPRGU_SPMI_MST_SW_RST 2327 28#define MT8195_TOPRGU_SW_RST_NUM 1629 30/* INFRA resets */31#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 032#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 133#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 234#define MT8195_INFRA_RST2_PCIE_P0_SWRST 335#define MT8195_INFRA_RST2_PCIE_P1_SWRST 436#define MT8195_INFRA_RST2_USBSIF_P1_SWRST 537 38/* VDOSYS1 */39#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 040#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 141#define MT8195_VDOSYS1_SW0_RST_B_GALS 242#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 343#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 444#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 545#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 646#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 747#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 848#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 949#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 1050#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 1151#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 1252#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 1353#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC 1454#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC 1555#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX 1656#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 1757#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 1858#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 1959#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 2060#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 2161#define MT8195_VDOSYS1_SW0_RST_B_DPI0 2262#define MT8195_VDOSYS1_SW0_RST_B_DPI1 2363#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR 2464#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 2565#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 2666#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 2767#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 2868#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 2969#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC 3070#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC 3171#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 3272#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 3373#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE 3474#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 4875#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 4976#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER 5077#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 5178#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 5279#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 5380#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 5481#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 5582 83#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */84