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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (C) 2023 Nuvoton Technologies.4 * Author: Chi-Fen Li <cfli0@nuvoton.com>5 *6 * Device Tree binding constants for MA35D1 reset controller.7 */8 9#ifndef __DT_BINDINGS_RESET_MA35D1_H10#define __DT_BINDINGS_RESET_MA35D1_H11 12#define MA35D1_RESET_CHIP 013#define MA35D1_RESET_CA35CR0 114#define MA35D1_RESET_CA35CR1 215#define MA35D1_RESET_CM4 316#define MA35D1_RESET_PDMA0 417#define MA35D1_RESET_PDMA1 518#define MA35D1_RESET_PDMA2 619#define MA35D1_RESET_PDMA3 720#define MA35D1_RESET_DISP 821#define MA35D1_RESET_VCAP0 922#define MA35D1_RESET_VCAP1 1023#define MA35D1_RESET_GFX 1124#define MA35D1_RESET_VDEC 1225#define MA35D1_RESET_WHC0 1326#define MA35D1_RESET_WHC1 1427#define MA35D1_RESET_GMAC0 1528#define MA35D1_RESET_GMAC1 1629#define MA35D1_RESET_HWSEM 1730#define MA35D1_RESET_EBI 1831#define MA35D1_RESET_HSUSBH0 1932#define MA35D1_RESET_HSUSBH1 2033#define MA35D1_RESET_HSUSBD 2134#define MA35D1_RESET_USBHL 2235#define MA35D1_RESET_SDH0 2336#define MA35D1_RESET_SDH1 2437#define MA35D1_RESET_NAND 2538#define MA35D1_RESET_GPIO 2639#define MA35D1_RESET_MCTLP 2740#define MA35D1_RESET_MCTLC 2841#define MA35D1_RESET_DDRPUB 2942#define MA35D1_RESET_TMR0 3043#define MA35D1_RESET_TMR1 3144#define MA35D1_RESET_TMR2 3245#define MA35D1_RESET_TMR3 3346#define MA35D1_RESET_I2C0 3447#define MA35D1_RESET_I2C1 3548#define MA35D1_RESET_I2C2 3649#define MA35D1_RESET_I2C3 3750#define MA35D1_RESET_QSPI0 3851#define MA35D1_RESET_SPI0 3952#define MA35D1_RESET_SPI1 4053#define MA35D1_RESET_SPI2 4154#define MA35D1_RESET_UART0 4255#define MA35D1_RESET_UART1 4356#define MA35D1_RESET_UART2 4457#define MA35D1_RESET_UART3 4558#define MA35D1_RESET_UART4 4659#define MA35D1_RESET_UART5 4760#define MA35D1_RESET_UART6 4861#define MA35D1_RESET_UART7 4962#define MA35D1_RESET_CANFD0 5063#define MA35D1_RESET_CANFD1 5164#define MA35D1_RESET_EADC0 5265#define MA35D1_RESET_I2S0 5366#define MA35D1_RESET_SC0 5467#define MA35D1_RESET_SC1 5568#define MA35D1_RESET_QSPI1 5669#define MA35D1_RESET_SPI3 5770#define MA35D1_RESET_EPWM0 5871#define MA35D1_RESET_EPWM1 5972#define MA35D1_RESET_QEI0 6073#define MA35D1_RESET_QEI1 6174#define MA35D1_RESET_ECAP0 6275#define MA35D1_RESET_ECAP1 6376#define MA35D1_RESET_CANFD2 6477#define MA35D1_RESET_ADC0 6578#define MA35D1_RESET_TMR4 6679#define MA35D1_RESET_TMR5 6780#define MA35D1_RESET_TMR6 6881#define MA35D1_RESET_TMR7 6982#define MA35D1_RESET_TMR8 7083#define MA35D1_RESET_TMR9 7184#define MA35D1_RESET_TMR10 7285#define MA35D1_RESET_TMR11 7386#define MA35D1_RESET_UART8 7487#define MA35D1_RESET_UART9 7588#define MA35D1_RESET_UART10 7689#define MA35D1_RESET_UART11 7790#define MA35D1_RESET_UART12 7891#define MA35D1_RESET_UART13 7992#define MA35D1_RESET_UART14 8093#define MA35D1_RESET_UART15 8194#define MA35D1_RESET_UART16 8295#define MA35D1_RESET_I2S1 8396#define MA35D1_RESET_I2C4 8497#define MA35D1_RESET_I2C5 8598#define MA35D1_RESET_EPWM2 8699#define MA35D1_RESET_ECAP2 87100#define MA35D1_RESET_QEI2 88101#define MA35D1_RESET_CANFD3 89102#define MA35D1_RESET_KPI 90103#define MA35D1_RESET_GIC 91104#define MA35D1_RESET_SSMCC 92105#define MA35D1_RESET_SSPCC 93106#define MA35D1_RESET_COUNT 94107 108#endif109