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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_RESET_IPQ_806X_H7#define _DT_BINDINGS_RESET_IPQ_806X_H8 9#define QDSS_STM_RESET 010#define AFAB_SMPSS_S_RESET 111#define AFAB_SMPSS_M1_RESET 212#define AFAB_SMPSS_M0_RESET 313#define AFAB_EBI1_CH0_RESET 414#define AFAB_EBI1_CH1_RESET 515#define SFAB_ADM0_M0_RESET 616#define SFAB_ADM0_M1_RESET 717#define SFAB_ADM0_M2_RESET 818#define ADM0_C2_RESET 919#define ADM0_C1_RESET 1020#define ADM0_C0_RESET 1121#define ADM0_PBUS_RESET 1222#define ADM0_RESET 1323#define QDSS_CLKS_SW_RESET 1424#define QDSS_POR_RESET 1525#define QDSS_TSCTR_RESET 1626#define QDSS_HRESET_RESET 1727#define QDSS_AXI_RESET 1828#define QDSS_DBG_RESET 1929#define SFAB_PCIE_M_RESET 2030#define SFAB_PCIE_S_RESET 2131#define PCIE_EXT_RESET 2232#define PCIE_PHY_RESET 2333#define PCIE_PCI_RESET 2434#define PCIE_POR_RESET 2535#define PCIE_HCLK_RESET 2636#define PCIE_ACLK_RESET 2737#define SFAB_LPASS_RESET 2838#define SFAB_AFAB_M_RESET 2939#define AFAB_SFAB_M0_RESET 3040#define AFAB_SFAB_M1_RESET 3141#define SFAB_SATA_S_RESET 3242#define SFAB_DFAB_M_RESET 3343#define DFAB_SFAB_M_RESET 3444#define DFAB_SWAY0_RESET 3545#define DFAB_SWAY1_RESET 3646#define DFAB_ARB0_RESET 3747#define DFAB_ARB1_RESET 3848#define PPSS_PROC_RESET 3949#define PPSS_RESET 4050#define DMA_BAM_RESET 4151#define SPS_TIC_H_RESET 4252#define SFAB_CFPB_M_RESET 4353#define SFAB_CFPB_S_RESET 4454#define TSIF_H_RESET 4555#define CE1_H_RESET 4656#define CE1_CORE_RESET 4757#define CE1_SLEEP_RESET 4858#define CE2_H_RESET 4959#define CE2_CORE_RESET 5060#define SFAB_SFPB_M_RESET 5161#define SFAB_SFPB_S_RESET 5262#define RPM_PROC_RESET 5363#define PMIC_SSBI2_RESET 5464#define SDC1_RESET 5565#define SDC2_RESET 5666#define SDC3_RESET 5767#define SDC4_RESET 5868#define USB_HS1_RESET 5969#define USB_HSIC_RESET 6070#define USB_FS1_XCVR_RESET 6171#define USB_FS1_RESET 6272#define GSBI1_RESET 6373#define GSBI2_RESET 6474#define GSBI3_RESET 6575#define GSBI4_RESET 6676#define GSBI5_RESET 6777#define GSBI6_RESET 6878#define GSBI7_RESET 6979#define SPDM_RESET 7080#define SEC_CTRL_RESET 7181#define TLMM_H_RESET 7282#define SFAB_SATA_M_RESET 7383#define SATA_RESET 7484#define TSSC_RESET 7585#define PDM_RESET 7686#define MPM_H_RESET 7787#define MPM_RESET 7888#define SFAB_SMPSS_S_RESET 7989#define PRNG_RESET 8090#define SFAB_CE3_M_RESET 8191#define SFAB_CE3_S_RESET 8292#define CE3_SLEEP_RESET 8393#define PCIE_1_M_RESET 8494#define PCIE_1_S_RESET 8595#define PCIE_1_EXT_RESET 8696#define PCIE_1_PHY_RESET 8797#define PCIE_1_PCI_RESET 8898#define PCIE_1_POR_RESET 8999#define PCIE_1_HCLK_RESET 90100#define PCIE_1_ACLK_RESET 91101#define PCIE_2_M_RESET 92102#define PCIE_2_S_RESET 93103#define PCIE_2_EXT_RESET 94104#define PCIE_2_PHY_RESET 95105#define PCIE_2_PCI_RESET 96106#define PCIE_2_POR_RESET 97107#define PCIE_2_HCLK_RESET 98108#define PCIE_2_ACLK_RESET 99109#define SFAB_USB30_S_RESET 100110#define SFAB_USB30_M_RESET 101111#define USB30_0_PORT2_HS_PHY_RESET 102112#define USB30_0_MASTER_RESET 103113#define USB30_0_SLEEP_RESET 104114#define USB30_0_UTMI_PHY_RESET 105115#define USB30_0_POWERON_RESET 106116#define USB30_0_PHY_RESET 107117#define USB30_1_MASTER_RESET 108118#define USB30_1_SLEEP_RESET 109119#define USB30_1_UTMI_PHY_RESET 110120#define USB30_1_POWERON_RESET 111121#define USB30_1_PHY_RESET 112122#define NSSFB0_RESET 113123#define NSSFB1_RESET 114124#define UBI32_CORE1_CLKRST_CLAMP_RESET 115125#define UBI32_CORE1_CLAMP_RESET 116126#define UBI32_CORE1_AHB_RESET 117127#define UBI32_CORE1_AXI_RESET 118128#define UBI32_CORE2_CLKRST_CLAMP_RESET 119129#define UBI32_CORE2_CLAMP_RESET 120130#define UBI32_CORE2_AHB_RESET 121131#define UBI32_CORE2_AXI_RESET 122132#define GMAC_CORE1_RESET 123133#define GMAC_CORE2_RESET 124134#define GMAC_CORE3_RESET 125135#define GMAC_CORE4_RESET 126136#define GMAC_AHB_RESET 127137#define NSS_CH0_RST_RX_CLK_N_RESET 128138#define NSS_CH0_RST_TX_CLK_N_RESET 129139#define NSS_CH0_RST_RX_125M_N_RESET 130140#define NSS_CH0_HW_RST_RX_125M_N_RESET 131141#define NSS_CH0_RST_TX_125M_N_RESET 132142#define NSS_CH1_RST_RX_CLK_N_RESET 133143#define NSS_CH1_RST_TX_CLK_N_RESET 134144#define NSS_CH1_RST_RX_125M_N_RESET 135145#define NSS_CH1_HW_RST_RX_125M_N_RESET 136146#define NSS_CH1_RST_TX_125M_N_RESET 137147#define NSS_CH2_RST_RX_CLK_N_RESET 138148#define NSS_CH2_RST_TX_CLK_N_RESET 139149#define NSS_CH2_RST_RX_125M_N_RESET 140150#define NSS_CH2_HW_RST_RX_125M_N_RESET 141151#define NSS_CH2_RST_TX_125M_N_RESET 142152#define NSS_CH3_RST_RX_CLK_N_RESET 143153#define NSS_CH3_RST_TX_CLK_N_RESET 144154#define NSS_CH3_RST_RX_125M_N_RESET 145155#define NSS_CH3_HW_RST_RX_125M_N_RESET 146156#define NSS_CH3_RST_TX_125M_N_RESET 147157#define NSS_RST_RX_250M_125M_N_RESET 148158#define NSS_RST_TX_250M_125M_N_RESET 149159#define NSS_QSGMII_TXPI_RST_N_RESET 150160#define NSS_QSGMII_CDR_RST_N_RESET 151161#define NSS_SGMII2_CDR_RST_N_RESET 152162#define NSS_SGMII3_CDR_RST_N_RESET 153163#define NSS_CAL_PRBS_RST_N_RESET 154164#define NSS_LCKDT_RST_N_RESET 155165#define NSS_SRDS_N_RESET 156166#define CRYPTO_ENG1_RESET 157167#define CRYPTO_ENG2_RESET 158168#define CRYPTO_ENG3_RESET 159169#define CRYPTO_ENG4_RESET 160170#define CRYPTO_AHB_RESET 161171 172#endif173