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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H7#define _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H8 9#define NSS_CC_SWITCH_CORE_ARES 110#define NSS_CC_APB_BRIDGE_ARES 211#define NSS_CC_MAC0_TX_ARES 312#define NSS_CC_MAC0_TX_SRDS1_ARES 413#define NSS_CC_MAC0_RX_ARES 514#define NSS_CC_MAC0_RX_SRDS1_ARES 615#define NSS_CC_MAC1_SRDS1_CH0_RX_ARES 716#define NSS_CC_MAC1_TX_ARES 817#define NSS_CC_MAC1_GEPHY0_TX_ARES 918#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES 1019#define NSS_CC_MAC1_SRDS1_CH0_TX_ARES 1120#define NSS_CC_MAC1_RX_ARES 1221#define NSS_CC_MAC1_GEPHY0_RX_ARES 1322#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES 1423#define NSS_CC_MAC2_SRDS1_CH1_RX_ARES 1524#define NSS_CC_MAC2_TX_ARES 1625#define NSS_CC_MAC2_GEPHY1_TX_ARES 1726#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES 1827#define NSS_CC_MAC2_SRDS1_CH1_TX_ARES 1928#define NSS_CC_MAC2_RX_ARES 2029#define NSS_CC_MAC2_GEPHY1_RX_ARES 2130#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES 2231#define NSS_CC_MAC3_SRDS1_CH2_RX_ARES 2332#define NSS_CC_MAC3_TX_ARES 2433#define NSS_CC_MAC3_GEPHY2_TX_ARES 2534#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES 2635#define NSS_CC_MAC3_SRDS1_CH2_TX_ARES 2736#define NSS_CC_MAC3_RX_ARES 2837#define NSS_CC_MAC3_GEPHY2_RX_ARES 2938#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES 3039#define NSS_CC_MAC4_SRDS1_CH3_RX_ARES 3140#define NSS_CC_MAC4_TX_ARES 3241#define NSS_CC_MAC4_GEPHY3_TX_ARES 3342#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES 3443#define NSS_CC_MAC4_SRDS1_CH3_TX_ARES 3544#define NSS_CC_MAC4_RX_ARES 3645#define NSS_CC_MAC4_GEPHY3_RX_ARES 3746#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES 3847#define NSS_CC_MAC5_TX_ARES 3948#define NSS_CC_MAC5_TX_SRDS0_ARES 4049#define NSS_CC_MAC5_RX_ARES 4150#define NSS_CC_MAC5_RX_SRDS0_ARES 4251#define NSS_CC_AHB_ARES 4352#define NSS_CC_SEC_CTRL_AHB_ARES 4453#define NSS_CC_TLMM_ARES 4554#define NSS_CC_TLMM_AHB_ARES 4655#define NSS_CC_CNOC_AHB_ARES 4756#define NSS_CC_MDIO_AHB_ARES 4857#define NSS_CC_MDIO_MASTER_AHB_ARES 4958#define NSS_CC_SRDS0_SYS_ARES 5059#define NSS_CC_SRDS1_SYS_ARES 5160#define NSS_CC_GEPHY0_SYS_ARES 5261#define NSS_CC_GEPHY1_SYS_ARES 5362#define NSS_CC_GEPHY2_SYS_ARES 5463#define NSS_CC_GEPHY3_SYS_ARES 5564#define NSS_CC_SEC_CTRL_ARES 5665#define NSS_CC_SEC_CTRL_SENSE_ARES 5766#define NSS_CC_SLEEP_ARES 5867#define NSS_CC_DEBUG_ARES 5968#define NSS_CC_GEPHY0_ARES 6069#define NSS_CC_GEPHY1_ARES 6170#define NSS_CC_GEPHY2_ARES 6271#define NSS_CC_GEPHY3_ARES 6372#define NSS_CC_DSP_ARES 6473#define NSS_CC_GEPHY_FULL_ARES 6574#define NSS_CC_GLOBAL_ARES 6675#define NSS_CC_XPCS_ARES 6776#endif77