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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/*3 * Copyright (c) 2023 Rockchip Electronics Co. Ltd.4 * Copyright (c) 2024 Collabora Ltd.5 *6 * Author: Elaine Zhang <zhangqing@rock-chips.com>7 * Author: Detlev Casanova <detlev.casanova@collabora.com>8 */9 10#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H11#define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H12 13#define SRST_A_TOP_BIU 014#define SRST_P_TOP_BIU 115#define SRST_A_TOP_MID_BIU 216#define SRST_A_SECURE_HIGH_BIU 317#define SRST_H_TOP_BIU 418 19#define SRST_H_VO0VOP_CHANNEL_BIU 520#define SRST_A_VO0VOP_CHANNEL_BIU 621 22#define SRST_BISRINTF 723 24#define SRST_H_AUDIO_BIU 825#define SRST_H_ASRC_2CH_0 926#define SRST_H_ASRC_2CH_1 1027#define SRST_H_ASRC_4CH_0 1128#define SRST_H_ASRC_4CH_1 1229#define SRST_ASRC_2CH_0 1330#define SRST_ASRC_2CH_1 1431#define SRST_ASRC_4CH_0 1532#define SRST_ASRC_4CH_1 1633#define SRST_M_SAI0_8CH 1734#define SRST_H_SAI0_8CH 1835#define SRST_H_SPDIF_RX0 1936#define SRST_M_SPDIF_RX0 2037 38#define SRST_H_SPDIF_RX1 2139#define SRST_M_SPDIF_RX1 2240#define SRST_M_SAI1_8CH 2341#define SRST_H_SAI1_8CH 2442#define SRST_M_SAI2_2CH 2543#define SRST_H_SAI2_2CH 2644#define SRST_M_SAI3_2CH 2745#define SRST_H_SAI3_2CH 2846 47#define SRST_M_SAI4_2CH 2948#define SRST_H_SAI4_2CH 3049#define SRST_H_ACDCDIG_DSM 3150#define SRST_M_ACDCDIG_DSM 3251#define SRST_PDM1 3352#define SRST_H_PDM1 3453#define SRST_M_PDM1 3554#define SRST_H_SPDIF_TX0 3655#define SRST_M_SPDIF_TX0 3756#define SRST_H_SPDIF_TX1 3857#define SRST_M_SPDIF_TX1 3958 59#define SRST_A_BUS_BIU 4060#define SRST_P_BUS_BIU 4161#define SRST_P_CRU 4262#define SRST_H_CAN0 4363#define SRST_CAN0 4464#define SRST_H_CAN1 4565#define SRST_CAN1 4666#define SRST_P_INTMUX2BUS 4767#define SRST_P_VCCIO_IOC 4868#define SRST_H_BUS_BIU 4969#define SRST_KEY_SHIFT 5070 71#define SRST_P_I2C1 5172#define SRST_P_I2C2 5273#define SRST_P_I2C3 5374#define SRST_P_I2C4 5475#define SRST_P_I2C5 5576#define SRST_P_I2C6 5677#define SRST_P_I2C7 5778#define SRST_P_I2C8 5879#define SRST_P_I2C9 5980#define SRST_P_WDT_BUSMCU 6081#define SRST_T_WDT_BUSMCU 6182#define SRST_A_GIC 6283#define SRST_I2C1 6384#define SRST_I2C2 6485#define SRST_I2C3 6586#define SRST_I2C4 6687 88#define SRST_I2C5 6789#define SRST_I2C6 6890#define SRST_I2C7 6991#define SRST_I2C8 7092#define SRST_I2C9 7193#define SRST_P_SARADC 7294#define SRST_SARADC 7395#define SRST_P_TSADC 7496#define SRST_TSADC 7597#define SRST_P_UART0 7698#define SRST_P_UART2 7799#define SRST_P_UART3 78100#define SRST_P_UART4 79101#define SRST_P_UART5 80102#define SRST_P_UART6 81103 104#define SRST_P_UART7 82105#define SRST_P_UART8 83106#define SRST_P_UART9 84107#define SRST_P_UART10 85108#define SRST_P_UART11 86109#define SRST_S_UART0 87110#define SRST_S_UART2 88111#define SRST_S_UART3 89112#define SRST_S_UART4 90113#define SRST_S_UART5 91114 115#define SRST_S_UART6 92116#define SRST_S_UART7 93117#define SRST_S_UART8 94118#define SRST_S_UART9 95119#define SRST_S_UART10 96120#define SRST_S_UART11 97121#define SRST_P_SPI0 98122#define SRST_P_SPI1 99123#define SRST_P_SPI2 100124 125#define SRST_P_SPI3 101126#define SRST_P_SPI4 102127#define SRST_SPI0 103128#define SRST_SPI1 104129#define SRST_SPI2 105130#define SRST_SPI3 106131#define SRST_SPI4 107132#define SRST_P_WDT0 108133#define SRST_T_WDT0 109134#define SRST_P_SYS_GRF 110135#define SRST_P_PWM1 111136#define SRST_PWM1 112137 138#define SRST_P_BUSTIMER0 113139#define SRST_P_BUSTIMER1 114140#define SRST_TIMER0 115141#define SRST_TIMER1 116142#define SRST_TIMER2 117143#define SRST_TIMER3 118144#define SRST_TIMER4 119145#define SRST_TIMER5 120146#define SRST_P_BUSIOC 121147#define SRST_P_MAILBOX0 122148#define SRST_P_GPIO1 123149 150#define SRST_GPIO1 124151#define SRST_P_GPIO2 125152#define SRST_GPIO2 126153#define SRST_P_GPIO3 127154#define SRST_GPIO3 128155#define SRST_P_GPIO4 129156#define SRST_GPIO4 130157#define SRST_A_DECOM 131158#define SRST_P_DECOM 132159#define SRST_D_DECOM 133160#define SRST_TIMER6 134161#define SRST_TIMER7 135162#define SRST_TIMER8 136163#define SRST_TIMER9 137164#define SRST_TIMER10 138165 166#define SRST_TIMER11 139167#define SRST_A_DMAC0 140168#define SRST_A_DMAC1 141169#define SRST_A_DMAC2 142170#define SRST_A_SPINLOCK 143171#define SRST_REF_PVTPLL_BUS 144172#define SRST_H_I3C0 145173#define SRST_H_I3C1 146174#define SRST_H_BUS_CM0_BIU 147175#define SRST_F_BUS_CM0_CORE 148176#define SRST_T_BUS_CM0_JTAG 149177 178#define SRST_P_INTMUX2PMU 150179#define SRST_P_INTMUX2DDR 151180#define SRST_P_PVTPLL_BUS 152181#define SRST_P_PWM2 153182#define SRST_PWM2 154183#define SRST_FREQ_PWM1 155184#define SRST_COUNTER_PWM1 156185#define SRST_I3C0 157186#define SRST_I3C1 158187 188#define SRST_P_DDR_MON_CH0 159189#define SRST_P_DDR_BIU 160190#define SRST_P_DDR_UPCTL_CH0 161191#define SRST_TM_DDR_MON_CH0 162192#define SRST_A_DDR_BIU 163193#define SRST_DFI_CH0 164194#define SRST_DDR_MON_CH0 165195#define SRST_P_DDR_HWLP_CH0 166196#define SRST_P_DDR_MON_CH1 167197#define SRST_P_DDR_HWLP_CH1 168198 199#define SRST_P_DDR_UPCTL_CH1 169200#define SRST_TM_DDR_MON_CH1 170201#define SRST_DFI_CH1 171202#define SRST_A_DDR01_MSCH0 172203#define SRST_A_DDR01_MSCH1 173204#define SRST_DDR_MON_CH1 174205#define SRST_DDR_SCRAMBLE_CH0 175206#define SRST_DDR_SCRAMBLE_CH1 176207#define SRST_P_AHB2APB 177208#define SRST_H_AHB2APB 178209#define SRST_H_DDR_BIU 179210#define SRST_F_DDR_CM0_CORE 180211 212#define SRST_P_DDR01_MSCH0 181213#define SRST_P_DDR01_MSCH1 182214#define SRST_DDR_TIMER0 183215#define SRST_DDR_TIMER1 184216#define SRST_T_WDT_DDR 185217#define SRST_P_WDT 186218#define SRST_P_TIMER 187219#define SRST_T_DDR_CM0_JTAG 188220#define SRST_P_DDR_GRF 189221 222#define SRST_DDR_UPCTL_CH0 190223#define SRST_A_DDR_UPCTL_0_CH0 191224#define SRST_A_DDR_UPCTL_1_CH0 192225#define SRST_A_DDR_UPCTL_2_CH0 193226#define SRST_A_DDR_UPCTL_3_CH0 194227#define SRST_A_DDR_UPCTL_4_CH0 195228 229#define SRST_DDR_UPCTL_CH1 196230#define SRST_A_DDR_UPCTL_0_CH1 197231#define SRST_A_DDR_UPCTL_1_CH1 198232#define SRST_A_DDR_UPCTL_2_CH1 199233#define SRST_A_DDR_UPCTL_3_CH1 200234#define SRST_A_DDR_UPCTL_4_CH1 201235 236#define SRST_REF_PVTPLL_DDR 202237#define SRST_P_PVTPLL_DDR 203238 239#define SRST_A_RKNN0 204240#define SRST_A_RKNN0_BIU 205241#define SRST_L_RKNN0_BIU 206242 243#define SRST_A_RKNN1 207244#define SRST_A_RKNN1_BIU 208245#define SRST_L_RKNN1_BIU 209246 247#define SRST_NPU_DAP 210248#define SRST_L_NPUSUBSYS_BIU 211249#define SRST_P_NPUTOP_BIU 212250#define SRST_P_NPU_TIMER 213251#define SRST_NPUTIMER0 214252#define SRST_NPUTIMER1 215253#define SRST_P_NPU_WDT 216254#define SRST_T_NPU_WDT 217255 256#define SRST_A_RKNN_CBUF 218257#define SRST_A_RVCORE0 219258#define SRST_P_NPU_GRF 220259#define SRST_P_PVTPLL_NPU 221260#define SRST_NPU_PVTPLL 222261#define SRST_H_NPU_CM0_BIU 223262#define SRST_F_NPU_CM0_CORE 224263#define SRST_T_NPU_CM0_JTAG 225264#define SRST_A_RKNNTOP_BIU 226265#define SRST_H_RKNN_CBUF 227266#define SRST_H_RKNNTOP_BIU 228267 268#define SRST_H_NVM_BIU 229269#define SRST_A_NVM_BIU 230270#define SRST_S_FSPI 231271#define SRST_H_FSPI 232272#define SRST_C_EMMC 233273#define SRST_H_EMMC 234274#define SRST_A_EMMC 235275#define SRST_B_EMMC 236276#define SRST_T_EMMC 237277 278#define SRST_P_GRF 238279#define SRST_P_PHP_BIU 239280#define SRST_A_PHP_BIU 240281#define SRST_P_PCIE0 241282#define SRST_PCIE0_POWER_UP 242283 284#define SRST_A_USB3OTG1 243285#define SRST_A_MMU0 244286#define SRST_A_SLV_MMU0 245287#define SRST_A_MMU1 246288 289#define SRST_A_SLV_MMU1 247290#define SRST_P_PCIE1 248291#define SRST_PCIE1_POWER_UP 249292 293#define SRST_RXOOB0 250294#define SRST_RXOOB1 251295#define SRST_PMALIVE0 252296#define SRST_PMALIVE1 253297#define SRST_A_SATA0 254298#define SRST_A_SATA1 255299#define SRST_ASIC1 256300#define SRST_ASIC0 257301 302#define SRST_P_CSIDPHY1 258303#define SRST_SCAN_CSIDPHY1 259304 305#define SRST_P_SDGMAC_GRF 260306#define SRST_P_SDGMAC_BIU 261307#define SRST_A_SDGMAC_BIU 262308#define SRST_H_SDGMAC_BIU 263309#define SRST_A_GMAC0 264310#define SRST_A_GMAC1 265311#define SRST_P_GMAC0 266312#define SRST_P_GMAC1 267313#define SRST_H_SDIO 268314 315#define SRST_H_SDMMC0 269316#define SRST_S_FSPI1 270317#define SRST_H_FSPI1 271318#define SRST_A_DSMC_BIU 272319#define SRST_A_DSMC 273320#define SRST_P_DSMC 274321#define SRST_H_HSGPIO 275322#define SRST_HSGPIO 276323#define SRST_A_HSGPIO 277324 325#define SRST_H_RKVDEC 278326#define SRST_H_RKVDEC_BIU 279327#define SRST_A_RKVDEC_BIU 280328#define SRST_RKVDEC_HEVC_CA 281329#define SRST_RKVDEC_CORE 282330 331#define SRST_A_USB_BIU 283332#define SRST_P_USBUFS_BIU 284333#define SRST_A_USB3OTG0 285334#define SRST_A_UFS_BIU 286335#define SRST_A_MMU2 287336#define SRST_A_SLV_MMU2 288337#define SRST_A_UFS_SYS 289338 339#define SRST_A_UFS 290340#define SRST_P_USBUFS_GRF 291341#define SRST_P_UFS_GRF 292342 343#define SRST_H_VPU_BIU 293344#define SRST_A_JPEG_BIU 294345#define SRST_A_RGA_BIU 295346#define SRST_A_VDPP_BIU 296347#define SRST_A_EBC_BIU 297348#define SRST_H_RGA2E_0 298349#define SRST_A_RGA2E_0 299350#define SRST_CORE_RGA2E_0 300351 352#define SRST_A_JPEG 301353#define SRST_H_JPEG 302354#define SRST_H_VDPP 303355#define SRST_A_VDPP 304356#define SRST_CORE_VDPP 305357#define SRST_H_RGA2E_1 306358#define SRST_A_RGA2E_1 307359#define SRST_CORE_RGA2E_1 308360#define SRST_H_EBC 309361#define SRST_A_EBC 310362#define SRST_D_EBC 311363 364#define SRST_H_VEPU0_BIU 312365#define SRST_A_VEPU0_BIU 313366#define SRST_H_VEPU0 314367#define SRST_A_VEPU0 315368#define SRST_VEPU0_CORE 316369 370#define SRST_A_VI_BIU 317371#define SRST_H_VI_BIU 318372#define SRST_P_VI_BIU 319373#define SRST_D_VICAP 320374#define SRST_A_VICAP 321375#define SRST_H_VICAP 322376#define SRST_ISP0 323377#define SRST_ISP0_VICAP 324378 379#define SRST_CORE_VPSS 325380#define SRST_P_CSI_HOST_0 326381#define SRST_P_CSI_HOST_1 327382#define SRST_P_CSI_HOST_2 328383#define SRST_P_CSI_HOST_3 329384#define SRST_P_CSI_HOST_4 330385 386#define SRST_CIFIN 331387#define SRST_VICAP_I0CLK 332388#define SRST_VICAP_I1CLK 333389#define SRST_VICAP_I2CLK 334390#define SRST_VICAP_I3CLK 335391#define SRST_VICAP_I4CLK 336392 393#define SRST_A_VOP_BIU 337394#define SRST_A_VOP2_BIU 338395#define SRST_H_VOP_BIU 339396#define SRST_P_VOP_BIU 340397#define SRST_H_VOP 341398#define SRST_A_VOP 342399#define SRST_D_VP0 343400 401#define SRST_D_VP1 344402#define SRST_D_VP2 345403#define SRST_P_VOP2_BIU 346404#define SRST_P_VOPGRF 347405 406#define SRST_H_VO0_BIU 348407#define SRST_P_VO0_BIU 349408#define SRST_A_HDCP0_BIU 350409#define SRST_P_VO0_GRF 351410#define SRST_A_HDCP0 352411#define SRST_H_HDCP0 353412#define SRST_HDCP0 354413 414#define SRST_P_DSIHOST0 355415#define SRST_DSIHOST0 356416#define SRST_P_HDMITX0 357417#define SRST_HDMITX0_REF 358418#define SRST_P_EDP0 359419#define SRST_EDP0_24M 360420 421#define SRST_M_SAI5_8CH 361422#define SRST_H_SAI5_8CH 362423#define SRST_M_SAI6_8CH 363424#define SRST_H_SAI6_8CH 364425#define SRST_H_SPDIF_TX2 365426#define SRST_M_SPDIF_TX2 366427#define SRST_H_SPDIF_RX2 367428#define SRST_M_SPDIF_RX2 368429 430#define SRST_H_SAI8_8CH 369431#define SRST_M_SAI8_8CH 370432 433#define SRST_H_VO1_BIU 371434#define SRST_P_VO1_BIU 372435#define SRST_M_SAI7_8CH 373436#define SRST_H_SAI7_8CH 374437#define SRST_H_SPDIF_TX3 375438#define SRST_H_SPDIF_TX4 376439#define SRST_H_SPDIF_TX5 377440#define SRST_M_SPDIF_TX3 378441 442#define SRST_DP0 379443#define SRST_P_VO1_GRF 380444#define SRST_A_HDCP1_BIU 381445#define SRST_A_HDCP1 382446#define SRST_H_HDCP1 383447#define SRST_HDCP1 384448#define SRST_H_SAI9_8CH 385449#define SRST_M_SAI9_8CH 386450#define SRST_M_SPDIF_TX4 387451#define SRST_M_SPDIF_TX5 388452 453#define SRST_GPU 389454#define SRST_A_S_GPU_BIU 390455#define SRST_A_M0_GPU_BIU 391456#define SRST_P_GPU_BIU 392457#define SRST_P_GPU_GRF 393458#define SRST_GPU_PVTPLL 394459#define SRST_P_PVTPLL_GPU 395460 461#define SRST_A_CENTER_BIU 396462#define SRST_A_DMA2DDR 397463#define SRST_A_DDR_SHAREMEM 398464#define SRST_A_DDR_SHAREMEM_BIU 399465#define SRST_H_CENTER_BIU 400466#define SRST_P_CENTER_GRF 401467#define SRST_P_DMA2DDR 402468#define SRST_P_SHAREMEM 403469#define SRST_P_CENTER_BIU 404470 471#define SRST_LINKSYM_HDMITXPHY0 405472 473#define SRST_DP0_PIXELCLK 406474#define SRST_PHY_DP0_TX 407475#define SRST_DP1_PIXELCLK 408476#define SRST_DP2_PIXELCLK 409477 478#define SRST_H_VEPU1_BIU 410479#define SRST_A_VEPU1_BIU 411480#define SRST_H_VEPU1 412481#define SRST_A_VEPU1 413482#define SRST_VEPU1_CORE 414483 484#define SRST_P_PHPPHY_CRU 415485#define SRST_P_APB2ASB_SLV_CHIP_TOP 416486#define SRST_P_PCIE2_COMBOPHY0 417487#define SRST_P_PCIE2_COMBOPHY0_GRF 418488#define SRST_P_PCIE2_COMBOPHY1 419489#define SRST_P_PCIE2_COMBOPHY1_GRF 420490 491#define SRST_PCIE0_PIPE_PHY 421492#define SRST_PCIE1_PIPE_PHY 422493 494#define SRST_H_CRYPTO_NS 423495#define SRST_H_TRNG_NS 424496#define SRST_P_OTPC_NS 425497#define SRST_OTPC_NS 426498 499#define SRST_P_HDPTX_GRF 427500#define SRST_P_HDPTX_APB 428501#define SRST_P_MIPI_DCPHY 429502#define SRST_P_DCPHY_GRF 430503#define SRST_P_BOT0_APB2ASB 431504#define SRST_P_BOT1_APB2ASB 432505#define SRST_USB2DEBUG 433506#define SRST_P_CSIPHY_GRF 434507#define SRST_P_CSIPHY 435508#define SRST_P_USBPHY_GRF_0 436509#define SRST_P_USBPHY_GRF_1 437510#define SRST_P_USBDP_GRF 438511#define SRST_P_USBDPPHY 439512#define SRST_USBDP_COMBO_PHY_INIT 440513 514#define SRST_USBDP_COMBO_PHY_CMN 441515#define SRST_USBDP_COMBO_PHY_LANE 442516#define SRST_USBDP_COMBO_PHY_PCS 443517#define SRST_M_MIPI_DCPHY 444518#define SRST_S_MIPI_DCPHY 445519#define SRST_SCAN_CSIPHY 446520#define SRST_P_VCCIO6_IOC 447521#define SRST_OTGPHY_0 448522#define SRST_OTGPHY_1 449523#define SRST_HDPTX_INIT 450524#define SRST_HDPTX_CMN 451525#define SRST_HDPTX_LANE 452526#define SRST_HDMITXHDP 453527 528#define SRST_MPHY_INIT 454529#define SRST_P_MPHY_GRF 455530#define SRST_P_VCCIO7_IOC 456531 532#define SRST_H_PMU1_BIU 457533#define SRST_P_PMU1_NIU 458534#define SRST_H_PMU_CM0_BIU 459535#define SRST_PMU_CM0_CORE 460536#define SRST_PMU_CM0_JTAG 461537 538#define SRST_P_CRU_PMU1 462539#define SRST_P_PMU1_GRF 463540#define SRST_P_PMU1_IOC 464541#define SRST_P_PMU1WDT 465542#define SRST_T_PMU1WDT 466543#define SRST_P_PMUTIMER 467544#define SRST_PMUTIMER0 468545#define SRST_PMUTIMER1 469546#define SRST_P_PMU1PWM 470547#define SRST_PMU1PWM 471548 549#define SRST_P_I2C0 472550#define SRST_I2C0 473551#define SRST_S_UART1 474552#define SRST_P_UART1 475553#define SRST_PDM0 476554#define SRST_H_PDM0 477555 556#define SRST_M_PDM0 478557#define SRST_H_VAD 479558 559#define SRST_P_PMU0GRF 480560#define SRST_P_PMU0IOC 481561#define SRST_P_GPIO0 482562#define SRST_DB_GPIO0 483563 564#endif565