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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/*3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.4 * Copyright (c) 2022 Collabora Ltd.5 *6 * Author: Elaine Zhang <zhangqing@rock-chips.com>7 * Author: Sebastian Reichel <sebastian.reichel@collabora.com>8 */9 10#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H11#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H12 13#define SRST_A_TOP_BIU 014#define SRST_P_TOP_BIU 115#define SRST_P_CSIPHY0 216#define SRST_CSIPHY0 317#define SRST_P_CSIPHY1 418#define SRST_CSIPHY1 519#define SRST_A_TOP_M500_BIU 620 21#define SRST_A_TOP_M400_BIU 722#define SRST_A_TOP_S200_BIU 823#define SRST_A_TOP_S400_BIU 924#define SRST_A_TOP_M300_BIU 1025#define SRST_USBDP_COMBO_PHY0_INIT 1126#define SRST_USBDP_COMBO_PHY0_CMN 1227#define SRST_USBDP_COMBO_PHY0_LANE 1328#define SRST_USBDP_COMBO_PHY0_PCS 1429#define SRST_USBDP_COMBO_PHY1_INIT 1530 31#define SRST_USBDP_COMBO_PHY1_CMN 1632#define SRST_USBDP_COMBO_PHY1_LANE 1733#define SRST_USBDP_COMBO_PHY1_PCS 1834#define SRST_DCPHY0 1935#define SRST_P_MIPI_DCPHY0 2036#define SRST_P_MIPI_DCPHY0_GRF 2137 38#define SRST_DCPHY1 2239#define SRST_P_MIPI_DCPHY1 2340#define SRST_P_MIPI_DCPHY1_GRF 2441#define SRST_P_APB2ASB_SLV_CDPHY 2542#define SRST_P_APB2ASB_SLV_CSIPHY 2643#define SRST_P_APB2ASB_SLV_VCCIO3_5 2744#define SRST_P_APB2ASB_SLV_VCCIO6 2845#define SRST_P_APB2ASB_SLV_EMMCIO 2946#define SRST_P_APB2ASB_SLV_IOC_TOP 3047#define SRST_P_APB2ASB_SLV_IOC_RIGHT 3148 49#define SRST_P_CRU 3250#define SRST_A_CHANNEL_SECURE2VO1USB 3351#define SRST_A_CHANNEL_SECURE2CENTER 3452#define SRST_H_CHANNEL_SECURE2VO1USB 3553#define SRST_H_CHANNEL_SECURE2CENTER 3654 55#define SRST_P_CHANNEL_SECURE2VO1USB 3756#define SRST_P_CHANNEL_SECURE2CENTER 3857 58#define SRST_H_AUDIO_BIU 3959#define SRST_P_AUDIO_BIU 4060#define SRST_H_I2S0_8CH 4161#define SRST_M_I2S0_8CH_TX 4262#define SRST_M_I2S0_8CH_RX 4363#define SRST_P_ACDCDIG 4464#define SRST_H_I2S2_2CH 4565#define SRST_H_I2S3_2CH 4666 67#define SRST_M_I2S2_2CH 4768#define SRST_M_I2S3_2CH 4869#define SRST_DAC_ACDCDIG 4970#define SRST_H_SPDIF0 5071 72#define SRST_M_SPDIF0 5173#define SRST_H_SPDIF1 5274#define SRST_M_SPDIF1 5375#define SRST_H_PDM1 5476#define SRST_PDM1 5577 78#define SRST_A_BUS_BIU 5679#define SRST_P_BUS_BIU 5780#define SRST_A_GIC 5881#define SRST_A_GIC_DBG 5982#define SRST_A_DMAC0 6083#define SRST_A_DMAC1 6184#define SRST_A_DMAC2 6285#define SRST_P_I2C1 6386#define SRST_P_I2C2 6487#define SRST_P_I2C3 6588#define SRST_P_I2C4 6689#define SRST_P_I2C5 6790#define SRST_P_I2C6 6891#define SRST_P_I2C7 6992#define SRST_P_I2C8 7093 94#define SRST_I2C1 7195#define SRST_I2C2 7296#define SRST_I2C3 7397#define SRST_I2C4 7498#define SRST_I2C5 7599#define SRST_I2C6 76100#define SRST_I2C7 77101#define SRST_I2C8 78102#define SRST_P_CAN0 79103#define SRST_CAN0 80104#define SRST_P_CAN1 81105#define SRST_CAN1 82106#define SRST_P_CAN2 83107#define SRST_CAN2 84108#define SRST_P_SARADC 85109 110#define SRST_P_TSADC 86111#define SRST_TSADC 87112#define SRST_P_UART1 88113#define SRST_P_UART2 89114#define SRST_P_UART3 90115#define SRST_P_UART4 91116#define SRST_P_UART5 92117#define SRST_P_UART6 93118#define SRST_P_UART7 94119#define SRST_P_UART8 95120#define SRST_P_UART9 96121#define SRST_S_UART1 97122 123#define SRST_S_UART2 98124#define SRST_S_UART3 99125#define SRST_S_UART4 100126#define SRST_S_UART5 101127#define SRST_S_UART6 102128#define SRST_S_UART7 103129 130#define SRST_S_UART8 104131#define SRST_S_UART9 105132#define SRST_P_SPI0 106133#define SRST_P_SPI1 107134#define SRST_P_SPI2 108135#define SRST_P_SPI3 109136#define SRST_P_SPI4 110137#define SRST_SPI0 111138#define SRST_SPI1 112139#define SRST_SPI2 113140#define SRST_SPI3 114141#define SRST_SPI4 115142 143#define SRST_P_WDT0 116144#define SRST_T_WDT0 117145#define SRST_P_SYS_GRF 118146#define SRST_P_PWM1 119147#define SRST_PWM1 120148#define SRST_P_PWM2 121149#define SRST_PWM2 122150#define SRST_P_PWM3 123151#define SRST_PWM3 124152#define SRST_P_BUSTIMER0 125153#define SRST_P_BUSTIMER1 126154#define SRST_BUSTIMER0 127155 156#define SRST_BUSTIMER1 128157#define SRST_BUSTIMER2 129158#define SRST_BUSTIMER3 130159#define SRST_BUSTIMER4 131160#define SRST_BUSTIMER5 132161#define SRST_BUSTIMER6 133162#define SRST_BUSTIMER7 134163#define SRST_BUSTIMER8 135164#define SRST_BUSTIMER9 136165#define SRST_BUSTIMER10 137166#define SRST_BUSTIMER11 138167#define SRST_P_MAILBOX0 139168#define SRST_P_MAILBOX1 140169#define SRST_P_MAILBOX2 141170#define SRST_P_GPIO1 142171#define SRST_GPIO1 143172 173#define SRST_P_GPIO2 144174#define SRST_GPIO2 145175#define SRST_P_GPIO3 146176#define SRST_GPIO3 147177#define SRST_P_GPIO4 148178#define SRST_GPIO4 149179#define SRST_A_DECOM 150180#define SRST_P_DECOM 151181#define SRST_D_DECOM 152182#define SRST_P_TOP 153183#define SRST_A_GICADB_GIC2CORE_BUS 154184#define SRST_P_DFT2APB 155185#define SRST_P_APB2ASB_MST_TOP 156186#define SRST_P_APB2ASB_MST_CDPHY 157187#define SRST_P_APB2ASB_MST_BOT_RIGHT 158188 189#define SRST_P_APB2ASB_MST_IOC_TOP 159190#define SRST_P_APB2ASB_MST_IOC_RIGHT 160191#define SRST_P_APB2ASB_MST_CSIPHY 161192#define SRST_P_APB2ASB_MST_VCCIO3_5 162193#define SRST_P_APB2ASB_MST_VCCIO6 163194#define SRST_P_APB2ASB_MST_EMMCIO 164195#define SRST_A_SPINLOCK 165196#define SRST_P_OTPC_NS 166197#define SRST_OTPC_NS 167198#define SRST_OTPC_ARB 168199 200#define SRST_P_BUSIOC 169201#define SRST_P_PMUCM0_INTMUX 170202#define SRST_P_DDRCM0_INTMUX 171203 204#define SRST_P_DDR_DFICTL_CH0 172205#define SRST_P_DDR_MON_CH0 173206#define SRST_P_DDR_STANDBY_CH0 174207#define SRST_P_DDR_UPCTL_CH0 175208#define SRST_TM_DDR_MON_CH0 176209#define SRST_P_DDR_GRF_CH01 177210#define SRST_DFI_CH0 178211#define SRST_SBR_CH0 179212#define SRST_DDR_UPCTL_CH0 180213#define SRST_DDR_DFICTL_CH0 181214#define SRST_DDR_MON_CH0 182215#define SRST_DDR_STANDBY_CH0 183216#define SRST_A_DDR_UPCTL_CH0 184217#define SRST_P_DDR_DFICTL_CH1 185218#define SRST_P_DDR_MON_CH1 186219#define SRST_P_DDR_STANDBY_CH1 187220 221#define SRST_P_DDR_UPCTL_CH1 188222#define SRST_TM_DDR_MON_CH1 189223#define SRST_DFI_CH1 190224#define SRST_SBR_CH1 191225#define SRST_DDR_UPCTL_CH1 192226#define SRST_DDR_DFICTL_CH1 193227#define SRST_DDR_MON_CH1 194228#define SRST_DDR_STANDBY_CH1 195229#define SRST_A_DDR_UPCTL_CH1 196230#define SRST_A_DDR01_MSCH0 197231#define SRST_A_DDR01_RS_MSCH0 198232#define SRST_A_DDR01_FRS_MSCH0 199233 234#define SRST_A_DDR01_SCRAMBLE0 200235#define SRST_A_DDR01_FRS_SCRAMBLE0 201236#define SRST_A_DDR01_MSCH1 202237#define SRST_A_DDR01_RS_MSCH1 203238#define SRST_A_DDR01_FRS_MSCH1 204239#define SRST_A_DDR01_SCRAMBLE1 205240#define SRST_A_DDR01_FRS_SCRAMBLE1 206241#define SRST_P_DDR01_MSCH0 207242#define SRST_P_DDR01_MSCH1 208243 244#define SRST_P_DDR_DFICTL_CH2 209245#define SRST_P_DDR_MON_CH2 210246#define SRST_P_DDR_STANDBY_CH2 211247#define SRST_P_DDR_UPCTL_CH2 212248#define SRST_TM_DDR_MON_CH2 213249#define SRST_P_DDR_GRF_CH23 214250#define SRST_DFI_CH2 215251#define SRST_SBR_CH2 216252#define SRST_DDR_UPCTL_CH2 217253#define SRST_DDR_DFICTL_CH2 218254#define SRST_DDR_MON_CH2 219255#define SRST_DDR_STANDBY_CH2 220256#define SRST_A_DDR_UPCTL_CH2 221257#define SRST_P_DDR_DFICTL_CH3 222258#define SRST_P_DDR_MON_CH3 223259#define SRST_P_DDR_STANDBY_CH3 224260 261#define SRST_P_DDR_UPCTL_CH3 225262#define SRST_TM_DDR_MON_CH3 226263#define SRST_DFI_CH3 227264#define SRST_SBR_CH3 228265#define SRST_DDR_UPCTL_CH3 229266#define SRST_DDR_DFICTL_CH3 230267#define SRST_DDR_MON_CH3 231268#define SRST_DDR_STANDBY_CH3 232269#define SRST_A_DDR_UPCTL_CH3 233270#define SRST_A_DDR23_MSCH2 234271#define SRST_A_DDR23_RS_MSCH2 235272#define SRST_A_DDR23_FRS_MSCH2 236273 274#define SRST_A_DDR23_SCRAMBLE2 237275#define SRST_A_DDR23_FRS_SCRAMBLE2 238276#define SRST_A_DDR23_MSCH3 239277#define SRST_A_DDR23_RS_MSCH3 240278#define SRST_A_DDR23_FRS_MSCH3 241279#define SRST_A_DDR23_SCRAMBLE3 242280#define SRST_A_DDR23_FRS_SCRAMBLE3 243281#define SRST_P_DDR23_MSCH2 244282#define SRST_P_DDR23_MSCH3 245283 284#define SRST_ISP1 246285#define SRST_ISP1_VICAP 247286#define SRST_A_ISP1_BIU 248287#define SRST_H_ISP1_BIU 249288 289#define SRST_A_RKNN1 250290#define SRST_A_RKNN1_BIU 251291#define SRST_H_RKNN1 252292#define SRST_H_RKNN1_BIU 253293 294#define SRST_A_RKNN2 254295#define SRST_A_RKNN2_BIU 255296#define SRST_H_RKNN2 256297#define SRST_H_RKNN2_BIU 257298 299#define SRST_A_RKNN_DSU0 258300#define SRST_P_NPUTOP_BIU 259301#define SRST_P_NPU_TIMER 260302#define SRST_NPUTIMER0 261303#define SRST_NPUTIMER1 262304#define SRST_P_NPU_WDT 263305#define SRST_T_NPU_WDT 264306#define SRST_P_NPU_PVTM 265307#define SRST_P_NPU_GRF 266308#define SRST_NPU_PVTM 267309 310#define SRST_NPU_PVTPLL 268311#define SRST_H_NPU_CM0_BIU 269312#define SRST_F_NPU_CM0_CORE 270313#define SRST_T_NPU_CM0_JTAG 271314#define SRST_A_RKNN0 272315#define SRST_A_RKNN0_BIU 273316#define SRST_H_RKNN0 274317#define SRST_H_RKNN0_BIU 275318 319#define SRST_H_NVM_BIU 276320#define SRST_A_NVM_BIU 277321#define SRST_H_EMMC 278322#define SRST_A_EMMC 279323#define SRST_C_EMMC 280324#define SRST_B_EMMC 281325#define SRST_T_EMMC 282326#define SRST_S_SFC 283327#define SRST_H_SFC 284328#define SRST_H_SFC_XIP 285329 330#define SRST_P_GRF 286331#define SRST_P_DEC_BIU 287332#define SRST_P_PHP_BIU 288333#define SRST_A_PCIE_GRIDGE 289334#define SRST_A_PHP_BIU 290335#define SRST_A_GMAC0 291336#define SRST_A_GMAC1 292337#define SRST_A_PCIE_BIU 293338#define SRST_PCIE0_POWER_UP 294339#define SRST_PCIE1_POWER_UP 295340#define SRST_PCIE2_POWER_UP 296341 342#define SRST_PCIE3_POWER_UP 297343#define SRST_PCIE4_POWER_UP 298344#define SRST_P_PCIE0 299345#define SRST_P_PCIE1 300346#define SRST_P_PCIE2 301347#define SRST_P_PCIE3 302348 349#define SRST_P_PCIE4 303350#define SRST_A_PHP_GIC_ITS 304351#define SRST_A_MMU_PCIE 305352#define SRST_A_MMU_PHP 306353#define SRST_A_MMU_BIU 307354 355#define SRST_A_USB3OTG2 308356 357#define SRST_PMALIVE0 309358#define SRST_PMALIVE1 310359#define SRST_PMALIVE2 311360#define SRST_A_SATA0 312361#define SRST_A_SATA1 313362#define SRST_A_SATA2 314363#define SRST_RXOOB0 315364#define SRST_RXOOB1 316365#define SRST_RXOOB2 317366#define SRST_ASIC0 318367#define SRST_ASIC1 319368#define SRST_ASIC2 320369 370#define SRST_A_RKVDEC_CCU 321371#define SRST_H_RKVDEC0 322372#define SRST_A_RKVDEC0 323373#define SRST_H_RKVDEC0_BIU 324374#define SRST_A_RKVDEC0_BIU 325375#define SRST_RKVDEC0_CA 326376#define SRST_RKVDEC0_HEVC_CA 327377#define SRST_RKVDEC0_CORE 328378 379#define SRST_H_RKVDEC1 329380#define SRST_A_RKVDEC1 330381#define SRST_H_RKVDEC1_BIU 331382#define SRST_A_RKVDEC1_BIU 332383#define SRST_RKVDEC1_CA 333384#define SRST_RKVDEC1_HEVC_CA 334385#define SRST_RKVDEC1_CORE 335386 387#define SRST_A_USB_BIU 336388#define SRST_H_USB_BIU 337389#define SRST_A_USB3OTG0 338390#define SRST_A_USB3OTG1 339391#define SRST_H_HOST0 340392#define SRST_H_HOST_ARB0 341393#define SRST_H_HOST1 342394#define SRST_H_HOST_ARB1 343395#define SRST_A_USB_GRF 344396#define SRST_C_USB2P0_HOST0 345397 398#define SRST_C_USB2P0_HOST1 346399#define SRST_HOST_UTMI0 347400#define SRST_HOST_UTMI1 348401 402#define SRST_A_VDPU_BIU 349403#define SRST_A_VDPU_LOW_BIU 350404#define SRST_H_VDPU_BIU 351405#define SRST_A_JPEG_DECODER_BIU 352406#define SRST_A_VPU 353407#define SRST_H_VPU 354408#define SRST_A_JPEG_ENCODER0 355409#define SRST_H_JPEG_ENCODER0 356410#define SRST_A_JPEG_ENCODER1 357411#define SRST_H_JPEG_ENCODER1 358412#define SRST_A_JPEG_ENCODER2 359413#define SRST_H_JPEG_ENCODER2 360414 415#define SRST_A_JPEG_ENCODER3 361416#define SRST_H_JPEG_ENCODER3 362417#define SRST_A_JPEG_DECODER 363418#define SRST_H_JPEG_DECODER 364419#define SRST_H_IEP2P0 365420#define SRST_A_IEP2P0 366421#define SRST_IEP2P0_CORE 367422#define SRST_H_RGA2 368423#define SRST_A_RGA2 369424#define SRST_RGA2_CORE 370425#define SRST_H_RGA3_0 371426#define SRST_A_RGA3_0 372427#define SRST_RGA3_0_CORE 373428 429#define SRST_H_RKVENC0_BIU 374430#define SRST_A_RKVENC0_BIU 375431#define SRST_H_RKVENC0 376432#define SRST_A_RKVENC0 377433#define SRST_RKVENC0_CORE 378434 435#define SRST_H_RKVENC1_BIU 379436#define SRST_A_RKVENC1_BIU 380437#define SRST_H_RKVENC1 381438#define SRST_A_RKVENC1 382439#define SRST_RKVENC1_CORE 383440 441#define SRST_A_VI_BIU 384442#define SRST_H_VI_BIU 385443#define SRST_P_VI_BIU 386444#define SRST_D_VICAP 387445#define SRST_A_VICAP 388446#define SRST_H_VICAP 389447#define SRST_ISP0 390448#define SRST_ISP0_VICAP 391449 450#define SRST_FISHEYE0 392451#define SRST_FISHEYE1 393452#define SRST_P_CSI_HOST_0 394453#define SRST_P_CSI_HOST_1 395454#define SRST_P_CSI_HOST_2 396455#define SRST_P_CSI_HOST_3 397456#define SRST_P_CSI_HOST_4 398457#define SRST_P_CSI_HOST_5 399458 459#define SRST_CSIHOST0_VICAP 400460#define SRST_CSIHOST1_VICAP 401461#define SRST_CSIHOST2_VICAP 402462#define SRST_CSIHOST3_VICAP 403463#define SRST_CSIHOST4_VICAP 404464#define SRST_CSIHOST5_VICAP 405465#define SRST_CIFIN 406466 467#define SRST_A_VOP_BIU 407468#define SRST_A_VOP_LOW_BIU 408469#define SRST_H_VOP_BIU 409470#define SRST_P_VOP_BIU 410471#define SRST_H_VOP 411472#define SRST_A_VOP 412473#define SRST_D_VOP0 413474#define SRST_D_VOP2HDMI_BRIDGE0 414475#define SRST_D_VOP2HDMI_BRIDGE1 415476 477#define SRST_D_VOP1 416478#define SRST_D_VOP2 417479#define SRST_D_VOP3 418480#define SRST_P_VOPGRF 419481#define SRST_P_DSIHOST0 420482#define SRST_P_DSIHOST1 421483#define SRST_DSIHOST0 422484#define SRST_DSIHOST1 423485#define SRST_VOP_PMU 424486#define SRST_P_VOP_CHANNEL_BIU 425487 488#define SRST_H_VO0_BIU 426489#define SRST_H_VO0_S_BIU 427490#define SRST_P_VO0_BIU 428491#define SRST_P_VO0_S_BIU 429492#define SRST_A_HDCP0_BIU 430493#define SRST_P_VO0GRF 431494#define SRST_H_HDCP_KEY0 432495#define SRST_A_HDCP0 433496#define SRST_H_HDCP0 434497#define SRST_HDCP0 435498 499#define SRST_P_TRNG0 436500#define SRST_DP0 437501#define SRST_DP1 438502#define SRST_H_I2S4_8CH 439503#define SRST_M_I2S4_8CH_TX 440504#define SRST_H_I2S8_8CH 441505 506#define SRST_M_I2S8_8CH_TX 442507#define SRST_H_SPDIF2_DP0 443508#define SRST_M_SPDIF2_DP0 444509#define SRST_H_SPDIF5_DP1 445510#define SRST_M_SPDIF5_DP1 446511 512#define SRST_A_HDCP1_BIU 447513#define SRST_A_VO1_BIU 448514#define SRST_H_VOP1_BIU 449515#define SRST_H_VOP1_S_BIU 450516#define SRST_P_VOP1_BIU 451517#define SRST_P_VO1GRF 452518#define SRST_P_VO1_S_BIU 453519 520#define SRST_H_I2S7_8CH 454521#define SRST_M_I2S7_8CH_RX 455522#define SRST_H_HDCP_KEY1 456523#define SRST_A_HDCP1 457524#define SRST_H_HDCP1 458525#define SRST_HDCP1 459526#define SRST_P_TRNG1 460527#define SRST_P_HDMITX0 461528 529#define SRST_HDMITX0_REF 462530#define SRST_P_HDMITX1 463531#define SRST_HDMITX1_REF 464532#define SRST_A_HDMIRX 465533#define SRST_P_HDMIRX 466534#define SRST_HDMIRX_REF 467535 536#define SRST_P_EDP0 468537#define SRST_EDP0_24M 469538#define SRST_P_EDP1 470539#define SRST_EDP1_24M 471540#define SRST_M_I2S5_8CH_TX 472541#define SRST_H_I2S5_8CH 473542#define SRST_M_I2S6_8CH_TX 474543 544#define SRST_M_I2S6_8CH_RX 475545#define SRST_H_I2S6_8CH 476546#define SRST_H_SPDIF3 477547#define SRST_M_SPDIF3 478548#define SRST_H_SPDIF4 479549#define SRST_M_SPDIF4 480550#define SRST_H_SPDIFRX0 481551#define SRST_M_SPDIFRX0 482552#define SRST_H_SPDIFRX1 483553#define SRST_M_SPDIFRX1 484554 555#define SRST_H_SPDIFRX2 485556#define SRST_M_SPDIFRX2 486557#define SRST_LINKSYM_HDMITXPHY0 487558#define SRST_LINKSYM_HDMITXPHY1 488559#define SRST_VO1_BRIDGE0 489560#define SRST_VO1_BRIDGE1 490561 562#define SRST_H_I2S9_8CH 491563#define SRST_M_I2S9_8CH_RX 492564#define SRST_H_I2S10_8CH 493565#define SRST_M_I2S10_8CH_RX 494566#define SRST_P_S_HDMIRX 495567 568#define SRST_GPU 496569#define SRST_SYS_GPU 497570#define SRST_A_S_GPU_BIU 498571#define SRST_A_M0_GPU_BIU 499572#define SRST_A_M1_GPU_BIU 500573#define SRST_A_M2_GPU_BIU 501574#define SRST_A_M3_GPU_BIU 502575#define SRST_P_GPU_BIU 503576#define SRST_P_GPU_PVTM 504577 578#define SRST_GPU_PVTM 505579#define SRST_P_GPU_GRF 506580#define SRST_GPU_PVTPLL 507581#define SRST_GPU_JTAG 508582 583#define SRST_A_AV1_BIU 509584#define SRST_A_AV1 510585#define SRST_P_AV1_BIU 511586#define SRST_P_AV1 512587 588#define SRST_A_DDR_BIU 513589#define SRST_A_DMA2DDR 514590#define SRST_A_DDR_SHAREMEM 515591#define SRST_A_DDR_SHAREMEM_BIU 516592#define SRST_A_CENTER_S200_BIU 517593#define SRST_A_CENTER_S400_BIU 518594#define SRST_H_AHB2APB 519595#define SRST_H_CENTER_BIU 520596#define SRST_F_DDR_CM0_CORE 521597 598#define SRST_DDR_TIMER0 522599#define SRST_DDR_TIMER1 523600#define SRST_T_WDT_DDR 524601#define SRST_T_DDR_CM0_JTAG 525602#define SRST_P_CENTER_GRF 526603#define SRST_P_AHB2APB 527604#define SRST_P_WDT 528605#define SRST_P_TIMER 529606#define SRST_P_DMA2DDR 530607#define SRST_P_SHAREMEM 531608#define SRST_P_CENTER_BIU 532609#define SRST_P_CENTER_CHANNEL_BIU 533610 611#define SRST_P_USBDPGRF0 534612#define SRST_P_USBDPPHY0 535613#define SRST_P_USBDPGRF1 536614#define SRST_P_USBDPPHY1 537615#define SRST_P_HDPTX0 538616#define SRST_P_HDPTX1 539617#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540618#define SRST_P_USB2PHY_U3_0_GRF0 541619#define SRST_P_USB2PHY_U3_1_GRF0 542620#define SRST_P_USB2PHY_U2_0_GRF0 543621#define SRST_P_USB2PHY_U2_1_GRF0 544622#define SRST_HDPTX0_ROPLL 545623#define SRST_HDPTX0_LCPLL 546624#define SRST_HDPTX0 547625#define SRST_HDPTX1_ROPLL 548626 627#define SRST_HDPTX1_LCPLL 549628#define SRST_HDPTX1 550629#define SRST_HDPTX0_HDMIRXPHY_SET 551630#define SRST_USBDP_COMBO_PHY0 552631#define SRST_USBDP_COMBO_PHY0_LCPLL 553632#define SRST_USBDP_COMBO_PHY0_ROPLL 554633#define SRST_USBDP_COMBO_PHY0_PCS_HS 555634#define SRST_USBDP_COMBO_PHY1 556635#define SRST_USBDP_COMBO_PHY1_LCPLL 557636#define SRST_USBDP_COMBO_PHY1_ROPLL 558637#define SRST_USBDP_COMBO_PHY1_PCS_HS 559638#define SRST_HDMIHDP0 560639#define SRST_HDMIHDP1 561640 641#define SRST_A_VO1USB_TOP_BIU 562642#define SRST_H_VO1USB_TOP_BIU 563643 644#define SRST_H_SDIO_BIU 564645#define SRST_H_SDIO 565646#define SRST_SDIO 566647 648#define SRST_H_RGA3_BIU 567649#define SRST_A_RGA3_BIU 568650#define SRST_H_RGA3_1 569651#define SRST_A_RGA3_1 570652#define SRST_RGA3_1_CORE 571653 654#define SRST_REF_PIPE_PHY0 572655#define SRST_REF_PIPE_PHY1 573656#define SRST_REF_PIPE_PHY2 574657 658#define SRST_P_PHPTOP_CRU 575659#define SRST_P_PCIE2_GRF0 576660#define SRST_P_PCIE2_GRF1 577661#define SRST_P_PCIE2_GRF2 578662#define SRST_P_PCIE2_PHY0 579663#define SRST_P_PCIE2_PHY1 580664#define SRST_P_PCIE2_PHY2 581665#define SRST_P_PCIE3_PHY 582666#define SRST_P_APB2ASB_SLV_CHIP_TOP 583667#define SRST_PCIE30_PHY 584668 669#define SRST_H_PMU1_BIU 585670#define SRST_P_PMU1_BIU 586671#define SRST_H_PMU_CM0_BIU 587672#define SRST_F_PMU_CM0_CORE 588673#define SRST_T_PMU1_CM0_JTAG 589674 675#define SRST_DDR_FAIL_SAFE 590676#define SRST_P_CRU_PMU1 591677#define SRST_P_PMU1_GRF 592678#define SRST_P_PMU1_IOC 593679#define SRST_P_PMU1WDT 594680#define SRST_T_PMU1WDT 595681#define SRST_P_PMU1TIMER 596682#define SRST_PMU1TIMER0 597683#define SRST_PMU1TIMER1 598684#define SRST_P_PMU1PWM 599685#define SRST_PMU1PWM 600686 687#define SRST_P_I2C0 601688#define SRST_I2C0 602689#define SRST_S_UART0 603690#define SRST_P_UART0 604691#define SRST_H_I2S1_8CH 605692#define SRST_M_I2S1_8CH_TX 606693#define SRST_M_I2S1_8CH_RX 607694#define SRST_H_PDM0 608695#define SRST_PDM0 609696 697#define SRST_H_VAD 610698#define SRST_HDPTX0_INIT 611699#define SRST_HDPTX0_CMN 612700#define SRST_HDPTX0_LANE 613701#define SRST_HDPTX1_INIT 614702 703#define SRST_HDPTX1_CMN 615704#define SRST_HDPTX1_LANE 616705#define SRST_M_MIPI_DCPHY0 617706#define SRST_S_MIPI_DCPHY0 618707#define SRST_M_MIPI_DCPHY1 619708#define SRST_S_MIPI_DCPHY1 620709#define SRST_OTGPHY_U3_0 621710#define SRST_OTGPHY_U3_1 622711#define SRST_OTGPHY_U2_0 623712#define SRST_OTGPHY_U2_1 624713 714#define SRST_P_PMU0GRF 625715#define SRST_P_PMU0IOC 626716#define SRST_P_GPIO0 627717#define SRST_GPIO0 628718 719#define SRST_A_SECURE_NS_BIU 629720#define SRST_H_SECURE_NS_BIU 630721#define SRST_A_SECURE_S_BIU 631722#define SRST_H_SECURE_S_BIU 632723#define SRST_P_SECURE_S_BIU 633724#define SRST_CRYPTO_CORE 634725 726#define SRST_CRYPTO_PKA 635727#define SRST_CRYPTO_RNG 636728#define SRST_A_CRYPTO 637729#define SRST_H_CRYPTO 638730#define SRST_KEYLADDER_CORE 639731#define SRST_KEYLADDER_RNG 640732#define SRST_A_KEYLADDER 641733#define SRST_H_KEYLADDER 642734#define SRST_P_OTPC_S 643735#define SRST_OTPC_S 644736#define SRST_WDT_S 645737 738#define SRST_T_WDT_S 646739#define SRST_H_BOOTROM 647740#define SRST_A_DCF 648741#define SRST_P_DCF 649742#define SRST_H_BOOTROM_NS 650743#define SRST_P_KEYLADDER 651744#define SRST_H_TRNG_S 652745 746#define SRST_H_TRNG_NS 653747#define SRST_D_SDMMC_BUFFER 654748#define SRST_H_SDMMC 655749#define SRST_H_SDMMC_BUFFER 656750#define SRST_SDMMC 657751#define SRST_P_TRNG_CHK 658752#define SRST_TRNG_S 659753 754#define SRST_A_HDMIRX_BIU 660755 756#endif757