88 lines · c
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */2/*3 * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.4 */5 6#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_7#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_8 9#define RST_MAIN_AP 010#define RST_RISCV_CPU 111#define RST_RISCV_LOW_SPEED_LOGIC 212#define RST_RISCV_CMN 313#define RST_HSDMA 414#define RST_SYSDMA 515#define RST_EFUSE0 616#define RST_EFUSE1 717#define RST_RTC 818#define RST_TIMER 919#define RST_WDT 1020#define RST_AHB_ROM0 1121#define RST_AHB_ROM1 1222#define RST_I2C0 1323#define RST_I2C1 1424#define RST_I2C2 1525#define RST_I2C3 1626#define RST_GPIO0 1727#define RST_GPIO1 1828#define RST_GPIO2 1929#define RST_PWM 2030#define RST_AXI_SRAM0 2131#define RST_AXI_SRAM1 2232#define RST_SF0 2333#define RST_SF1 2434#define RST_LPC 2535#define RST_ETH0 2636#define RST_EMMC 2737#define RST_SD 2838#define RST_UART0 2939#define RST_UART1 3040#define RST_UART2 3141#define RST_UART3 3242#define RST_SPI0 3343#define RST_SPI1 3444#define RST_DBG_I2C 3545#define RST_PCIE0 3646#define RST_PCIE1 3747#define RST_DDR0 3848#define RST_DDR1 3949#define RST_DDR2 4050#define RST_DDR3 4151#define RST_FAU0 4252#define RST_FAU1 4353#define RST_FAU2 4454#define RST_RXU0 4555#define RST_RXU1 4656#define RST_RXU2 4757#define RST_RXU3 4858#define RST_RXU4 4959#define RST_RXU5 5060#define RST_RXU6 5161#define RST_RXU7 5262#define RST_RXU8 5363#define RST_RXU9 5464#define RST_RXU10 5565#define RST_RXU11 5666#define RST_RXU12 5767#define RST_RXU13 5868#define RST_RXU14 5969#define RST_RXU15 6070#define RST_RXU16 6171#define RST_RXU17 6272#define RST_RXU18 6373#define RST_RXU19 6474#define RST_RXU20 6575#define RST_RXU21 6676#define RST_RXU22 6777#define RST_RXU23 6878#define RST_RXU24 6979#define RST_RXU25 7080#define RST_RXU26 7181#define RST_RXU27 7282#define RST_RXU28 7383#define RST_RXU29 7484#define RST_RXU30 7585#define RST_RXU31 7686 87#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */88