168 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */2/*3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved4 * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>5 */6 7#ifndef _DT_BINDINGS_STM32MP25_RESET_H_8#define _DT_BINDINGS_STM32MP25_RESET_H_9 10#define TIM1_R 011#define TIM2_R 112#define TIM3_R 213#define TIM4_R 314#define TIM5_R 415#define TIM6_R 516#define TIM7_R 617#define TIM8_R 718#define TIM10_R 819#define TIM11_R 920#define TIM12_R 1021#define TIM13_R 1122#define TIM14_R 1223#define TIM15_R 1324#define TIM16_R 1425#define TIM17_R 1526#define TIM20_R 1627#define LPTIM1_R 1728#define LPTIM2_R 1829#define LPTIM3_R 1930#define LPTIM4_R 2031#define LPTIM5_R 2132#define SPI1_R 2233#define SPI2_R 2334#define SPI3_R 2435#define SPI4_R 2536#define SPI5_R 2637#define SPI6_R 2738#define SPI7_R 2839#define SPI8_R 2940#define SPDIFRX_R 3041#define USART1_R 3142#define USART2_R 3243#define USART3_R 3344#define UART4_R 3445#define UART5_R 3546#define USART6_R 3647#define UART7_R 3748#define UART8_R 3849#define UART9_R 3950#define LPUART1_R 4051#define IS2M_R 4152#define I2C1_R 4253#define I2C2_R 4354#define I2C3_R 4455#define I2C4_R 4556#define I2C5_R 4657#define I2C6_R 4758#define I2C7_R 4859#define I2C8_R 4960#define SAI1_R 5061#define SAI2_R 5162#define SAI3_R 5263#define SAI4_R 5364#define MDF1_R 5465#define MDF2_R 5566#define FDCAN_R 5667#define HDP_R 5768#define ADC12_R 5869#define ADC3_R 5970#define ETH1_R 6071#define ETH2_R 6172#define USBH_R 6273#define USB2PHY1_R 6374#define USB2PHY2_R 6475#define USB3DR_R 6576#define USB3PCIEPHY_R 6677#define USBTC_R 6778#define ETHSW_R 6879#define SDMMC1_R 6980#define SDMMC1DLL_R 7081#define SDMMC2_R 7182#define SDMMC2DLL_R 7283#define SDMMC3_R 7384#define SDMMC3DLL_R 7485#define GPU_R 7586#define LTDC_R 7687#define DSI_R 7788#define LVDS_R 7889#define CSI_R 7990#define DCMIPP_R 8091#define CCI_R 8192#define VDEC_R 8293#define VENC_R 8394#define WWDG1_R 8495#define WWDG2_R 8596#define VREF_R 8697#define DTS_R 8798#define CRC_R 8899#define SERC_R 89100#define OSPIIOM_R 90101#define I3C1_R 91102#define I3C2_R 92103#define I3C3_R 93104#define I3C4_R 94105#define IWDG2_KER_R 95106#define IWDG4_KER_R 96107#define RNG_R 97108#define PKA_R 98109#define SAES_R 99110#define HASH_R 100111#define CRYP1_R 101112#define CRYP2_R 102113#define PCIE_R 103114#define OSPI1_R 104115#define OSPI1DLL_R 105116#define OSPI2_R 106117#define OSPI2DLL_R 107118#define FMC_R 108119#define DBG_R 109120#define GPIOA_R 110121#define GPIOB_R 111122#define GPIOC_R 112123#define GPIOD_R 113124#define GPIOE_R 114125#define GPIOF_R 115126#define GPIOG_R 116127#define GPIOH_R 117128#define GPIOI_R 118129#define GPIOJ_R 119130#define GPIOK_R 120131#define GPIOZ_R 121132#define HPDMA1_R 122133#define HPDMA2_R 123134#define HPDMA3_R 124135#define LPDMA_R 125136#define HSEM_R 126137#define IPCC1_R 127138#define IPCC2_R 128139#define C2_HOLDBOOT_R 129140#define C1_HOLDBOOT_R 130141#define C1_R 131142#define C1P1POR_R 132143#define C1P1_R 133144#define C2_R 134145#define C3_R 135146#define SYS_R 136147#define VSW_R 137148#define C1MS_R 138149#define DDRCP_R 139150#define DDRCAPB_R 140151#define DDRPHYCAPB_R 141152#define DDRCFG_R 142153#define DDR_R 143154 155#define STM32MP25_LAST_RESET 144156 157#define RST_SCMI_C1_R 0158#define RST_SCMI_C2_R 1159#define RST_SCMI_C1_HOLDBOOT_R 2160#define RST_SCMI_C2_HOLDBOOT_R 3161#define RST_SCMI_FMC 4162#define RST_SCMI_OSPI1 5163#define RST_SCMI_OSPI1DLL 6164#define RST_SCMI_OSPI2 7165#define RST_SCMI_OSPI2DLL 8166 167#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */168