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1/* SPDX-License-Identifier: GPL-2.0 OR MIT */2/*3 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>4 * Copyright (C) 2022 StarFive Technology Co., Ltd.5 */6 7#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__8#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__9 10/* SYSCRG resets */11#define JH7110_SYSRST_JTAG_APB 012#define JH7110_SYSRST_SYSCON_APB 113#define JH7110_SYSRST_IOMUX_APB 214#define JH7110_SYSRST_BUS 315#define JH7110_SYSRST_DEBUG 416#define JH7110_SYSRST_CORE0 517#define JH7110_SYSRST_CORE1 618#define JH7110_SYSRST_CORE2 719#define JH7110_SYSRST_CORE3 820#define JH7110_SYSRST_CORE4 921#define JH7110_SYSRST_CORE0_ST 1022#define JH7110_SYSRST_CORE1_ST 1123#define JH7110_SYSRST_CORE2_ST 1224#define JH7110_SYSRST_CORE3_ST 1325#define JH7110_SYSRST_CORE4_ST 1426#define JH7110_SYSRST_TRACE0 1527#define JH7110_SYSRST_TRACE1 1628#define JH7110_SYSRST_TRACE2 1729#define JH7110_SYSRST_TRACE3 1830#define JH7110_SYSRST_TRACE4 1931#define JH7110_SYSRST_TRACE_COM 2032#define JH7110_SYSRST_GPU_APB 2133#define JH7110_SYSRST_GPU_DOMA 2234#define JH7110_SYSRST_NOC_BUS_APB 2335#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 2436#define JH7110_SYSRST_NOC_BUS_CPU_AXI 2537#define JH7110_SYSRST_NOC_BUS_DISP_AXI 2638#define JH7110_SYSRST_NOC_BUS_GPU_AXI 2739#define JH7110_SYSRST_NOC_BUS_ISP_AXI 2840#define JH7110_SYSRST_NOC_BUS_DDRC 2941#define JH7110_SYSRST_NOC_BUS_STG_AXI 3042#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 3143 44#define JH7110_SYSRST_NOC_BUS_VENC_AXI 3245#define JH7110_SYSRST_AXI_CFG1_AHB 3346#define JH7110_SYSRST_AXI_CFG1_MAIN 3447#define JH7110_SYSRST_AXI_CFG0_MAIN 3548#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 3649#define JH7110_SYSRST_AXI_CFG0_HIFI4 3750#define JH7110_SYSRST_DDR_AXI 3851#define JH7110_SYSRST_DDR_OSC 3952#define JH7110_SYSRST_DDR_APB 4053#define JH7110_SYSRST_ISP_TOP 4154#define JH7110_SYSRST_ISP_TOP_AXI 4255#define JH7110_SYSRST_VOUT_TOP_SRC 4356#define JH7110_SYSRST_CODAJ12_AXI 4457#define JH7110_SYSRST_CODAJ12_CORE 4558#define JH7110_SYSRST_CODAJ12_APB 4659#define JH7110_SYSRST_WAVE511_AXI 4760#define JH7110_SYSRST_WAVE511_BPU 4861#define JH7110_SYSRST_WAVE511_VCE 4962#define JH7110_SYSRST_WAVE511_APB 5063#define JH7110_SYSRST_VDEC_JPG 5164#define JH7110_SYSRST_VDEC_MAIN 5265#define JH7110_SYSRST_AXIMEM0_AXI 5366#define JH7110_SYSRST_WAVE420L_AXI 5467#define JH7110_SYSRST_WAVE420L_BPU 5568#define JH7110_SYSRST_WAVE420L_VCE 5669#define JH7110_SYSRST_WAVE420L_APB 5770#define JH7110_SYSRST_AXIMEM1_AXI 5871#define JH7110_SYSRST_AXIMEM2_AXI 5972#define JH7110_SYSRST_INTMEM 6073#define JH7110_SYSRST_QSPI_AHB 6174#define JH7110_SYSRST_QSPI_APB 6275#define JH7110_SYSRST_QSPI_REF 6376 77#define JH7110_SYSRST_SDIO0_AHB 6478#define JH7110_SYSRST_SDIO1_AHB 6579#define JH7110_SYSRST_GMAC1_AXI 6680#define JH7110_SYSRST_GMAC1_AHB 6781#define JH7110_SYSRST_MAILBOX_APB 6882#define JH7110_SYSRST_SPI0_APB 6983#define JH7110_SYSRST_SPI1_APB 7084#define JH7110_SYSRST_SPI2_APB 7185#define JH7110_SYSRST_SPI3_APB 7286#define JH7110_SYSRST_SPI4_APB 7387#define JH7110_SYSRST_SPI5_APB 7488#define JH7110_SYSRST_SPI6_APB 7589#define JH7110_SYSRST_I2C0_APB 7690#define JH7110_SYSRST_I2C1_APB 7791#define JH7110_SYSRST_I2C2_APB 7892#define JH7110_SYSRST_I2C3_APB 7993#define JH7110_SYSRST_I2C4_APB 8094#define JH7110_SYSRST_I2C5_APB 8195#define JH7110_SYSRST_I2C6_APB 8296#define JH7110_SYSRST_UART0_APB 8397#define JH7110_SYSRST_UART0_CORE 8498#define JH7110_SYSRST_UART1_APB 8599#define JH7110_SYSRST_UART1_CORE 86100#define JH7110_SYSRST_UART2_APB 87101#define JH7110_SYSRST_UART2_CORE 88102#define JH7110_SYSRST_UART3_APB 89103#define JH7110_SYSRST_UART3_CORE 90104#define JH7110_SYSRST_UART4_APB 91105#define JH7110_SYSRST_UART4_CORE 92106#define JH7110_SYSRST_UART5_APB 93107#define JH7110_SYSRST_UART5_CORE 94108#define JH7110_SYSRST_SPDIF_APB 95109 110#define JH7110_SYSRST_PWMDAC_APB 96111#define JH7110_SYSRST_PDM_DMIC 97112#define JH7110_SYSRST_PDM_APB 98113#define JH7110_SYSRST_I2SRX_APB 99114#define JH7110_SYSRST_I2SRX_BCLK 100115#define JH7110_SYSRST_I2STX0_APB 101116#define JH7110_SYSRST_I2STX0_BCLK 102117#define JH7110_SYSRST_I2STX1_APB 103118#define JH7110_SYSRST_I2STX1_BCLK 104119#define JH7110_SYSRST_TDM_AHB 105120#define JH7110_SYSRST_TDM_CORE 106121#define JH7110_SYSRST_TDM_APB 107122#define JH7110_SYSRST_PWM_APB 108123#define JH7110_SYSRST_WDT_APB 109124#define JH7110_SYSRST_WDT_CORE 110125#define JH7110_SYSRST_CAN0_APB 111126#define JH7110_SYSRST_CAN0_CORE 112127#define JH7110_SYSRST_CAN0_TIMER 113128#define JH7110_SYSRST_CAN1_APB 114129#define JH7110_SYSRST_CAN1_CORE 115130#define JH7110_SYSRST_CAN1_TIMER 116131#define JH7110_SYSRST_TIMER_APB 117132#define JH7110_SYSRST_TIMER0 118133#define JH7110_SYSRST_TIMER1 119134#define JH7110_SYSRST_TIMER2 120135#define JH7110_SYSRST_TIMER3 121136#define JH7110_SYSRST_INT_CTRL_APB 122137#define JH7110_SYSRST_TEMP_APB 123138#define JH7110_SYSRST_TEMP_CORE 124139#define JH7110_SYSRST_JTAG_CERTIFICATION 125140 141#define JH7110_SYSRST_END 126142 143/* AONCRG resets */144#define JH7110_AONRST_GMAC0_AXI 0145#define JH7110_AONRST_GMAC0_AHB 1146#define JH7110_AONRST_IOMUX 2147#define JH7110_AONRST_PMU_APB 3148#define JH7110_AONRST_PMU_WKUP 4149#define JH7110_AONRST_RTC_APB 5150#define JH7110_AONRST_RTC_CAL 6151#define JH7110_AONRST_RTC_32K 7152 153#define JH7110_AONRST_END 8154 155/* STGCRG resets */156#define JH7110_STGRST_SYSCON 0157#define JH7110_STGRST_HIFI4_CORE 1158#define JH7110_STGRST_HIFI4_AXI 2159#define JH7110_STGRST_SEC_AHB 3160#define JH7110_STGRST_E24_CORE 4161#define JH7110_STGRST_DMA1P_AXI 5162#define JH7110_STGRST_DMA1P_AHB 6163#define JH7110_STGRST_USB0_AXI 7164#define JH7110_STGRST_USB0_APB 8165#define JH7110_STGRST_USB0_UTMI_APB 9166#define JH7110_STGRST_USB0_PWRUP 10167#define JH7110_STGRST_PCIE0_AXI_MST0 11168#define JH7110_STGRST_PCIE0_AXI_SLV0 12169#define JH7110_STGRST_PCIE0_AXI_SLV 13170#define JH7110_STGRST_PCIE0_BRG 14171#define JH7110_STGRST_PCIE0_CORE 15172#define JH7110_STGRST_PCIE0_APB 16173#define JH7110_STGRST_PCIE1_AXI_MST0 17174#define JH7110_STGRST_PCIE1_AXI_SLV0 18175#define JH7110_STGRST_PCIE1_AXI_SLV 19176#define JH7110_STGRST_PCIE1_BRG 20177#define JH7110_STGRST_PCIE1_CORE 21178#define JH7110_STGRST_PCIE1_APB 22179 180#define JH7110_STGRST_END 23181 182/* ISPCRG resets */183#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0184#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1185#define JH7110_ISPRST_M31DPHY_HW 2186#define JH7110_ISPRST_M31DPHY_B09_AON 3187#define JH7110_ISPRST_VIN_APB 4188#define JH7110_ISPRST_VIN_PIXEL_IF0 5189#define JH7110_ISPRST_VIN_PIXEL_IF1 6190#define JH7110_ISPRST_VIN_PIXEL_IF2 7191#define JH7110_ISPRST_VIN_PIXEL_IF3 8192#define JH7110_ISPRST_VIN_SYS 9193#define JH7110_ISPRST_VIN_P_AXI_RD 10194#define JH7110_ISPRST_VIN_P_AXI_WR 11195 196#define JH7110_ISPRST_END 12197 198/* VOUTCRG resets */199#define JH7110_VOUTRST_DC8200_AXI 0200#define JH7110_VOUTRST_DC8200_AHB 1201#define JH7110_VOUTRST_DC8200_CORE 2202#define JH7110_VOUTRST_DSITX_DPI 3203#define JH7110_VOUTRST_DSITX_APB 4204#define JH7110_VOUTRST_DSITX_RXESC 5205#define JH7110_VOUTRST_DSITX_SYS 6206#define JH7110_VOUTRST_DSITX_TXBYTEHS 7207#define JH7110_VOUTRST_DSITX_TXESC 8208#define JH7110_VOUTRST_HDMI_TX_HDMI 9209#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10210#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11211 212#define JH7110_VOUTRST_END 12213 214#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */215