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1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */2/*3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>4 */5 6#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_7#define _DT_BINDINGS_RESET_SUN50I_H6_H_8 9#define RST_MBUS 010#define RST_BUS_DE 111#define RST_BUS_DEINTERLACE 212#define RST_BUS_GPU 313#define RST_BUS_CE 414#define RST_BUS_VE 515#define RST_BUS_EMCE 616#define RST_BUS_VP9 717#define RST_BUS_DMA 818#define RST_BUS_MSGBOX 919#define RST_BUS_SPINLOCK 1020#define RST_BUS_HSTIMER 1121#define RST_BUS_DBG 1222#define RST_BUS_PSI 1323#define RST_BUS_PWM 1424#define RST_BUS_IOMMU 1525#define RST_BUS_DRAM 1626#define RST_BUS_NAND 1727#define RST_BUS_MMC0 1828#define RST_BUS_MMC1 1929#define RST_BUS_MMC2 2030#define RST_BUS_UART0 2131#define RST_BUS_UART1 2232#define RST_BUS_UART2 2333#define RST_BUS_UART3 2434#define RST_BUS_I2C0 2535#define RST_BUS_I2C1 2636#define RST_BUS_I2C2 2737#define RST_BUS_I2C3 2838#define RST_BUS_SCR0 2939#define RST_BUS_SCR1 3040#define RST_BUS_SPI0 3141#define RST_BUS_SPI1 3242#define RST_BUS_EMAC 3343#define RST_BUS_TS 3444#define RST_BUS_IR_TX 3545#define RST_BUS_THS 3646#define RST_BUS_I2S0 3747#define RST_BUS_I2S1 3848#define RST_BUS_I2S2 3949#define RST_BUS_I2S3 4050#define RST_BUS_SPDIF 4151#define RST_BUS_DMIC 4252#define RST_BUS_AUDIO_HUB 4353#define RST_USB_PHY0 4454#define RST_USB_PHY1 4555#define RST_USB_PHY3 4656#define RST_USB_HSIC 4757#define RST_BUS_OHCI0 4858#define RST_BUS_OHCI3 4959#define RST_BUS_EHCI0 5060#define RST_BUS_XHCI 5161#define RST_BUS_EHCI3 5262#define RST_BUS_OTG 5363#define RST_BUS_PCIE 5464#define RST_PCIE_POWERUP 5565#define RST_BUS_HDMI 5666#define RST_BUS_HDMI_SUB 5767#define RST_BUS_TCON_TOP 5868#define RST_BUS_TCON_LCD0 5969#define RST_BUS_TCON_TV0 6070#define RST_BUS_CSI 6171#define RST_BUS_HDCP 6272 73#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */74