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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.4 */5 6#ifndef _ABI_MACH_T186_RESET_T186_H_7#define _ABI_MACH_T186_RESET_T186_H_8 9 10#define TEGRA186_RESET_ACTMON 011#define TEGRA186_RESET_AFI 112#define TEGRA186_RESET_CEC 213#define TEGRA186_RESET_CSITE 314#define TEGRA186_RESET_DP2 415#define TEGRA186_RESET_DPAUX 516#define TEGRA186_RESET_DSI 617#define TEGRA186_RESET_DSIB 718#define TEGRA186_RESET_DTV 819#define TEGRA186_RESET_DVFS 920#define TEGRA186_RESET_ENTROPY 1021#define TEGRA186_RESET_EXTPERIPH1 1122#define TEGRA186_RESET_EXTPERIPH2 1223#define TEGRA186_RESET_EXTPERIPH3 1324#define TEGRA186_RESET_GPU 1425#define TEGRA186_RESET_HDA 1526#define TEGRA186_RESET_HDA2CODEC_2X 1627#define TEGRA186_RESET_HDA2HDMICODEC 1728#define TEGRA186_RESET_HOST1X 1829#define TEGRA186_RESET_I2C1 1930#define TEGRA186_RESET_I2C2 2031#define TEGRA186_RESET_I2C3 2132#define TEGRA186_RESET_I2C4 2233#define TEGRA186_RESET_I2C5 2334#define TEGRA186_RESET_I2C6 2435#define TEGRA186_RESET_ISP 2536#define TEGRA186_RESET_KFUSE 2637#define TEGRA186_RESET_LA 2738#define TEGRA186_RESET_MIPI_CAL 2839#define TEGRA186_RESET_PCIE 2940#define TEGRA186_RESET_PCIEXCLK 3041#define TEGRA186_RESET_SATA 3142#define TEGRA186_RESET_SATACOLD 3243#define TEGRA186_RESET_SDMMC1 3344#define TEGRA186_RESET_SDMMC2 3445#define TEGRA186_RESET_SDMMC3 3546#define TEGRA186_RESET_SDMMC4 3647#define TEGRA186_RESET_SE 3748#define TEGRA186_RESET_SOC_THERM 3849#define TEGRA186_RESET_SOR0 3950#define TEGRA186_RESET_SPI1 4051#define TEGRA186_RESET_SPI2 4152#define TEGRA186_RESET_SPI3 4253#define TEGRA186_RESET_SPI4 4354#define TEGRA186_RESET_TMR 4455#define TEGRA186_RESET_TRIG_SYS 4556#define TEGRA186_RESET_TSEC 4657#define TEGRA186_RESET_UARTA 4758#define TEGRA186_RESET_UARTB 4859#define TEGRA186_RESET_UARTC 4960#define TEGRA186_RESET_UARTD 5061#define TEGRA186_RESET_VI 5162#define TEGRA186_RESET_VIC 5263#define TEGRA186_RESET_XUSB_DEV 5364#define TEGRA186_RESET_XUSB_HOST 5465#define TEGRA186_RESET_XUSB_PADCTL 5566#define TEGRA186_RESET_XUSB_SS 5667#define TEGRA186_RESET_AON_APB 5768#define TEGRA186_RESET_AXI_CBB 5869#define TEGRA186_RESET_BPMP_APB 5970#define TEGRA186_RESET_CAN1 6071#define TEGRA186_RESET_CAN2 6172#define TEGRA186_RESET_DMIC5 6273#define TEGRA186_RESET_DSIC 6374#define TEGRA186_RESET_DSID 6475#define TEGRA186_RESET_EMC_EMC 6576#define TEGRA186_RESET_EMC_MEM 6677#define TEGRA186_RESET_EMCSB_EMC 6778#define TEGRA186_RESET_EMCSB_MEM 6879#define TEGRA186_RESET_EQOS 6980#define TEGRA186_RESET_GPCDMA 7081#define TEGRA186_RESET_GPIO_CTL0 7182#define TEGRA186_RESET_GPIO_CTL1 7283#define TEGRA186_RESET_GPIO_CTL2 7384#define TEGRA186_RESET_GPIO_CTL3 7485#define TEGRA186_RESET_GPIO_CTL4 7586#define TEGRA186_RESET_GPIO_CTL5 7687#define TEGRA186_RESET_I2C10 7788#define TEGRA186_RESET_I2C12 7889#define TEGRA186_RESET_I2C13 7990#define TEGRA186_RESET_I2C14 8091#define TEGRA186_RESET_I2C7 8192#define TEGRA186_RESET_I2C8 8293#define TEGRA186_RESET_I2C9 8394#define TEGRA186_RESET_JTAG2AXI 8495#define TEGRA186_RESET_MPHY_IOBIST 8596#define TEGRA186_RESET_MPHY_L0_RX 8697#define TEGRA186_RESET_MPHY_L0_TX 8798#define TEGRA186_RESET_NVCSI 8899#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89100#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90101#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91102#define TEGRA186_RESET_NVDISPLAY0_MISC 92103#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93104#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94105#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95106#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96107#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97108#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98109#define TEGRA186_RESET_PWM1 99110#define TEGRA186_RESET_PWM2 100111#define TEGRA186_RESET_PWM3 101112#define TEGRA186_RESET_PWM4 102113#define TEGRA186_RESET_PWM5 103114#define TEGRA186_RESET_PWM6 104115#define TEGRA186_RESET_PWM7 105116#define TEGRA186_RESET_PWM8 106117#define TEGRA186_RESET_SCE_APB 107118#define TEGRA186_RESET_SOR1 108119#define TEGRA186_RESET_TACH 109120#define TEGRA186_RESET_TSC 110121#define TEGRA186_RESET_UARTF 111122#define TEGRA186_RESET_UARTG 112123#define TEGRA186_RESET_UFSHC 113124#define TEGRA186_RESET_UFSHC_AXI_M 114125#define TEGRA186_RESET_UPHY 115126#define TEGRA186_RESET_ADSP 116127#define TEGRA186_RESET_ADSPDBG 117128#define TEGRA186_RESET_ADSPINTF 118129#define TEGRA186_RESET_ADSPNEON 119130#define TEGRA186_RESET_ADSPPERIPH 120131#define TEGRA186_RESET_ADSPSCU 121132#define TEGRA186_RESET_ADSPWDT 122133#define TEGRA186_RESET_APE 123134#define TEGRA186_RESET_DPAUX1 124135#define TEGRA186_RESET_NVDEC 125136#define TEGRA186_RESET_NVENC 126137#define TEGRA186_RESET_NVJPG 127138#define TEGRA186_RESET_PEX_USB_UPHY 128139#define TEGRA186_RESET_QSPI 129140#define TEGRA186_RESET_TSECB 130141#define TEGRA186_RESET_VI_I2C 131142#define TEGRA186_RESET_UARTE 132143#define TEGRA186_RESET_TOP_GTE 133144#define TEGRA186_RESET_SHSP 134145#define TEGRA186_RESET_PEX_USB_UPHY_L5 135146#define TEGRA186_RESET_PEX_USB_UPHY_L4 136147#define TEGRA186_RESET_PEX_USB_UPHY_L3 137148#define TEGRA186_RESET_PEX_USB_UPHY_L2 138149#define TEGRA186_RESET_PEX_USB_UPHY_L1 139150#define TEGRA186_RESET_PEX_USB_UPHY_L0 140151#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141152#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142153#define TEGRA186_RESET_TSCTNVI 143154#define TEGRA186_RESET_EXTPERIPH4 144155#define TEGRA186_RESET_DSIPADCTL 145156#define TEGRA186_RESET_AUD_MCLK 146157#define TEGRA186_RESET_MPHY_CLK_CTL 147158#define TEGRA186_RESET_MPHY_L1_RX 148159#define TEGRA186_RESET_MPHY_L1_TX 149160#define TEGRA186_RESET_UFSHC_LP 150161#define TEGRA186_RESET_BPMP_NIC 151162#define TEGRA186_RESET_BPMP_NSYSPORESET 152163#define TEGRA186_RESET_BPMP_NRESET 153164#define TEGRA186_RESET_BPMP_DBGRESETN 154165#define TEGRA186_RESET_BPMP_PRESETDBGN 155166#define TEGRA186_RESET_BPMP_PM 156167#define TEGRA186_RESET_BPMP_CVC 157168#define TEGRA186_RESET_BPMP_DMA 158169#define TEGRA186_RESET_BPMP_HSP 159170#define TEGRA186_RESET_TSCTNBPMP 160171#define TEGRA186_RESET_BPMP_TKE 161172#define TEGRA186_RESET_BPMP_GTE 162173#define TEGRA186_RESET_BPMP_PM_ACTMON 163174#define TEGRA186_RESET_AON_NIC 164175#define TEGRA186_RESET_AON_NSYSPORESET 165176#define TEGRA186_RESET_AON_NRESET 166177#define TEGRA186_RESET_AON_DBGRESETN 167178#define TEGRA186_RESET_AON_PRESETDBGN 168179#define TEGRA186_RESET_AON_ACTMON 169180#define TEGRA186_RESET_AOPM 170181#define TEGRA186_RESET_AOVC 171182#define TEGRA186_RESET_AON_DMA 172183#define TEGRA186_RESET_AON_GPIO 173184#define TEGRA186_RESET_AON_HSP 174185#define TEGRA186_RESET_TSCTNAON 175186#define TEGRA186_RESET_AON_TKE 176187#define TEGRA186_RESET_AON_GTE 177188#define TEGRA186_RESET_SCE_NIC 178189#define TEGRA186_RESET_SCE_NSYSPORESET 179190#define TEGRA186_RESET_SCE_NRESET 180191#define TEGRA186_RESET_SCE_DBGRESETN 181192#define TEGRA186_RESET_SCE_PRESETDBGN 182193#define TEGRA186_RESET_SCE_ACTMON 183194#define TEGRA186_RESET_SCE_PM 184195#define TEGRA186_RESET_SCE_DMA 185196#define TEGRA186_RESET_SCE_HSP 186197#define TEGRA186_RESET_TSCTNSCE 187198#define TEGRA186_RESET_SCE_TKE 188199#define TEGRA186_RESET_SCE_GTE 189200#define TEGRA186_RESET_SCE_CFG 190201#define TEGRA186_RESET_ADSP_ALL 191202/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */203#define TEGRA186_RESET_UFSHC_LP_SEQ 192204#define TEGRA186_RESET_SIZE 193205 206#endif207