153 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */3 4#ifndef __ABI_MACH_T194_RESET_H5#define __ABI_MACH_T194_RESET_H6 7#define TEGRA194_RESET_ACTMON 18#define TEGRA194_RESET_ADSP_ALL 29#define TEGRA194_RESET_AFI 310#define TEGRA194_RESET_CAN1 411#define TEGRA194_RESET_CAN2 512#define TEGRA194_RESET_DLA0 613#define TEGRA194_RESET_DLA1 714#define TEGRA194_RESET_DPAUX 815#define TEGRA194_RESET_DPAUX1 916#define TEGRA194_RESET_DPAUX2 1017#define TEGRA194_RESET_DPAUX3 1118#define TEGRA194_RESET_EQOS 1719#define TEGRA194_RESET_GPCDMA 1820#define TEGRA194_RESET_GPU 1921#define TEGRA194_RESET_HDA 2022#define TEGRA194_RESET_HDA2CODEC_2X 2123#define TEGRA194_RESET_HDA2HDMICODEC 2224#define TEGRA194_RESET_HOST1X 2325#define TEGRA194_RESET_I2C1 2426#define TEGRA194_RESET_I2C10 2527#define TEGRA194_RESET_RSVD_26 2628#define TEGRA194_RESET_RSVD_27 2729#define TEGRA194_RESET_RSVD_28 2830#define TEGRA194_RESET_I2C2 2931#define TEGRA194_RESET_I2C3 3032#define TEGRA194_RESET_I2C4 3133#define TEGRA194_RESET_I2C6 3234#define TEGRA194_RESET_I2C7 3335#define TEGRA194_RESET_I2C8 3436#define TEGRA194_RESET_I2C9 3537#define TEGRA194_RESET_ISP 3638#define TEGRA194_RESET_MIPI_CAL 3739#define TEGRA194_RESET_MPHY_CLK_CTL 3840#define TEGRA194_RESET_MPHY_L0_RX 3941#define TEGRA194_RESET_MPHY_L0_TX 4042#define TEGRA194_RESET_MPHY_L1_RX 4143#define TEGRA194_RESET_MPHY_L1_TX 4244#define TEGRA194_RESET_NVCSI 4345#define TEGRA194_RESET_NVDEC 4446#define TEGRA194_RESET_NVDISPLAY0_HEAD0 4547#define TEGRA194_RESET_NVDISPLAY0_HEAD1 4648#define TEGRA194_RESET_NVDISPLAY0_HEAD2 4749#define TEGRA194_RESET_NVDISPLAY0_HEAD3 4850#define TEGRA194_RESET_NVDISPLAY0_MISC 4951#define TEGRA194_RESET_NVDISPLAY0_WGRP0 5052#define TEGRA194_RESET_NVDISPLAY0_WGRP1 5153#define TEGRA194_RESET_NVDISPLAY0_WGRP2 5254#define TEGRA194_RESET_NVDISPLAY0_WGRP3 5355#define TEGRA194_RESET_NVDISPLAY0_WGRP4 5456#define TEGRA194_RESET_NVDISPLAY0_WGRP5 5557#define TEGRA194_RESET_RSVD_56 5658#define TEGRA194_RESET_RSVD_57 5759#define TEGRA194_RESET_RSVD_58 5860#define TEGRA194_RESET_NVENC 5961#define TEGRA194_RESET_NVENC1 6062#define TEGRA194_RESET_NVJPG 6163#define TEGRA194_RESET_PCIE 6264#define TEGRA194_RESET_PCIEXCLK 6365#define TEGRA194_RESET_RSVD_64 6466#define TEGRA194_RESET_RSVD_65 6567#define TEGRA194_RESET_PVA0_ALL 6668#define TEGRA194_RESET_PVA1_ALL 6769#define TEGRA194_RESET_PWM1 6870#define TEGRA194_RESET_PWM2 6971#define TEGRA194_RESET_PWM3 7072#define TEGRA194_RESET_PWM4 7173#define TEGRA194_RESET_PWM5 7274#define TEGRA194_RESET_PWM6 7375#define TEGRA194_RESET_PWM7 7476#define TEGRA194_RESET_PWM8 7577#define TEGRA194_RESET_QSPI0 7678#define TEGRA194_RESET_QSPI1 7779#define TEGRA194_RESET_SATA 7880#define TEGRA194_RESET_SATACOLD 7981#define TEGRA194_RESET_SCE_ALL 8082#define TEGRA194_RESET_RCE_ALL 8183#define TEGRA194_RESET_SDMMC1 8284#define TEGRA194_RESET_RSVD_83 8385#define TEGRA194_RESET_SDMMC3 8486#define TEGRA194_RESET_SDMMC4 8587#define TEGRA194_RESET_SE 8688#define TEGRA194_RESET_SOR0 8789#define TEGRA194_RESET_SOR1 8890#define TEGRA194_RESET_SOR2 8991#define TEGRA194_RESET_SOR3 9092#define TEGRA194_RESET_SPI1 9193#define TEGRA194_RESET_SPI2 9294#define TEGRA194_RESET_SPI3 9395#define TEGRA194_RESET_SPI4 9496#define TEGRA194_RESET_TACH 9597#define TEGRA194_RESET_RSVD_96 9698#define TEGRA194_RESET_TSCTNVI 9799#define TEGRA194_RESET_TSEC 98100#define TEGRA194_RESET_TSECB 99101#define TEGRA194_RESET_UARTA 100102#define TEGRA194_RESET_UARTB 101103#define TEGRA194_RESET_UARTC 102104#define TEGRA194_RESET_UARTD 103105#define TEGRA194_RESET_UARTE 104106#define TEGRA194_RESET_UARTF 105107#define TEGRA194_RESET_UARTG 106108#define TEGRA194_RESET_UARTH 107109#define TEGRA194_RESET_UFSHC 108110#define TEGRA194_RESET_UFSHC_AXI_M 109111#define TEGRA194_RESET_UFSHC_LP_SEQ 110112#define TEGRA194_RESET_RSVD_111 111113#define TEGRA194_RESET_VI 112114#define TEGRA194_RESET_VIC 113115#define TEGRA194_RESET_XUSB_PADCTL 114116#define TEGRA194_RESET_NVDEC1 115117#define TEGRA194_RESET_PEX0_CORE_0 116118#define TEGRA194_RESET_PEX0_CORE_1 117119#define TEGRA194_RESET_PEX0_CORE_2 118120#define TEGRA194_RESET_PEX0_CORE_3 119121#define TEGRA194_RESET_PEX0_CORE_4 120122#define TEGRA194_RESET_PEX0_CORE_0_APB 121123#define TEGRA194_RESET_PEX0_CORE_1_APB 122124#define TEGRA194_RESET_PEX0_CORE_2_APB 123125#define TEGRA194_RESET_PEX0_CORE_3_APB 124126#define TEGRA194_RESET_PEX0_CORE_4_APB 125127#define TEGRA194_RESET_PEX0_COMMON_APB 126128#define TEGRA194_RESET_PEX1_CORE_5 129129#define TEGRA194_RESET_PEX1_CORE_5_APB 130130#define TEGRA194_RESET_CVNAS 131131#define TEGRA194_RESET_CVNAS_FCM 132132#define TEGRA194_RESET_DMIC5 144133#define TEGRA194_RESET_APE 145134#define TEGRA194_RESET_PEX_USB_UPHY 146135#define TEGRA194_RESET_PEX_USB_UPHY_L0 147136#define TEGRA194_RESET_PEX_USB_UPHY_L1 148137#define TEGRA194_RESET_PEX_USB_UPHY_L2 149138#define TEGRA194_RESET_PEX_USB_UPHY_L3 150139#define TEGRA194_RESET_PEX_USB_UPHY_L4 151140#define TEGRA194_RESET_PEX_USB_UPHY_L5 152141#define TEGRA194_RESET_PEX_USB_UPHY_L6 153142#define TEGRA194_RESET_PEX_USB_UPHY_L7 154143#define TEGRA194_RESET_PEX_USB_UPHY_L8 155144#define TEGRA194_RESET_PEX_USB_UPHY_L9 156145#define TEGRA194_RESET_PEX_USB_UPHY_L10 157146#define TEGRA194_RESET_PEX_USB_UPHY_L11 158147#define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159148#define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160149#define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161150#define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162151 152#endif153