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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */3 4#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H5#define DT_BINDINGS_RESET_TEGRA234_RESET_H6 7/**8 * @file9 * @defgroup bpmp_reset_ids Reset ID's10 * @brief Identifiers for Resets controllable by firmware11 * @{12 */13#define TEGRA234_RESET_ACTMON 1U14#define TEGRA234_RESET_ADSP_ALL 2U15#define TEGRA234_RESET_DSI_CORE 3U16#define TEGRA234_RESET_CAN1 4U17#define TEGRA234_RESET_CAN2 5U18#define TEGRA234_RESET_DLA0 6U19#define TEGRA234_RESET_DLA1 7U20#define TEGRA234_RESET_DPAUX 8U21#define TEGRA234_RESET_OFA 9U22#define TEGRA234_RESET_NVJPG1 10U23#define TEGRA234_RESET_PEX1_CORE_6 11U24#define TEGRA234_RESET_PEX1_CORE_6_APB 12U25#define TEGRA234_RESET_PEX1_COMMON_APB 13U26#define TEGRA234_RESET_PEX2_CORE_7 14U27#define TEGRA234_RESET_PEX2_CORE_7_APB 15U28#define TEGRA234_RESET_NVDISPLAY 16U29#define TEGRA234_RESET_EQOS 17U30#define TEGRA234_RESET_GPCDMA 18U31#define TEGRA234_RESET_GPU 19U32#define TEGRA234_RESET_HDA 20U33#define TEGRA234_RESET_HDACODEC 21U34#define TEGRA234_RESET_EQOS_MACSEC 22U35#define TEGRA234_RESET_EQOS_MACSEC_SECURE 23U36#define TEGRA234_RESET_I2C1 24U37#define TEGRA234_RESET_PEX2_CORE_8 25U38#define TEGRA234_RESET_PEX2_CORE_8_APB 26U39#define TEGRA234_RESET_PEX2_CORE_9 27U40#define TEGRA234_RESET_PEX2_CORE_9_APB 28U41#define TEGRA234_RESET_I2C2 29U42#define TEGRA234_RESET_I2C3 30U43#define TEGRA234_RESET_I2C4 31U44#define TEGRA234_RESET_I2C6 32U45#define TEGRA234_RESET_I2C7 33U46#define TEGRA234_RESET_I2C8 34U47#define TEGRA234_RESET_I2C9 35U48#define TEGRA234_RESET_ISP 36U49#define TEGRA234_RESET_MIPI_CAL 37U50#define TEGRA234_RESET_MPHY_CLK_CTL 38U51#define TEGRA234_RESET_MPHY_L0_RX 39U52#define TEGRA234_RESET_MPHY_L0_TX 40U53#define TEGRA234_RESET_MPHY_L1_RX 41U54#define TEGRA234_RESET_MPHY_L1_TX 42U55#define TEGRA234_RESET_NVCSI 43U56#define TEGRA234_RESET_NVDEC 44U57#define TEGRA234_RESET_MGBE0_PCS 45U58#define TEGRA234_RESET_MGBE0_MAC 46U59#define TEGRA234_RESET_MGBE0_MACSEC 47U60#define TEGRA234_RESET_MGBE0_MACSEC_SECURE 48U61#define TEGRA234_RESET_MGBE1_PCS 49U62#define TEGRA234_RESET_MGBE1_MAC 50U63#define TEGRA234_RESET_MGBE1_MACSEC 51U64#define TEGRA234_RESET_MGBE1_MACSEC_SECURE 52U65#define TEGRA234_RESET_MGBE2_PCS 53U66#define TEGRA234_RESET_MGBE2_MAC 54U67#define TEGRA234_RESET_MGBE2_MACSEC 55U68#define TEGRA234_RESET_PEX2_CORE_10 56U69#define TEGRA234_RESET_PEX2_CORE_10_APB 57U70#define TEGRA234_RESET_PEX2_COMMON_APB 58U71#define TEGRA234_RESET_NVENC 59U72#define TEGRA234_RESET_MGBE2_MACSEC_SECURE 60U73#define TEGRA234_RESET_NVJPG 61U74#define TEGRA234_RESET_LA 64U75#define TEGRA234_RESET_HWPM 65U76#define TEGRA234_RESET_PVA0_ALL 66U77#define TEGRA234_RESET_CEC 67U78#define TEGRA234_RESET_PWM1 68U79#define TEGRA234_RESET_PWM2 69U80#define TEGRA234_RESET_PWM3 70U81#define TEGRA234_RESET_PWM4 71U82#define TEGRA234_RESET_PWM5 72U83#define TEGRA234_RESET_PWM6 73U84#define TEGRA234_RESET_PWM7 74U85#define TEGRA234_RESET_PWM8 75U86#define TEGRA234_RESET_QSPI0 76U87#define TEGRA234_RESET_QSPI1 77U88#define TEGRA234_RESET_I2S7 78U89#define TEGRA234_RESET_I2S8 79U90#define TEGRA234_RESET_SCE_ALL 80U91#define TEGRA234_RESET_RCE_ALL 81U92#define TEGRA234_RESET_SDMMC1 82U93#define TEGRA234_RESET_RSVD_83 83U94#define TEGRA234_RESET_RSVD_84 84U95#define TEGRA234_RESET_SDMMC4 85U96#define TEGRA234_RESET_MGBE3_PCS 87U97#define TEGRA234_RESET_MGBE3_MAC 88U98#define TEGRA234_RESET_MGBE3_MACSEC 89U99#define TEGRA234_RESET_MGBE3_MACSEC_SECURE 90U100#define TEGRA234_RESET_SPI1 91U101#define TEGRA234_RESET_SPI2 92U102#define TEGRA234_RESET_SPI3 93U103#define TEGRA234_RESET_SPI4 94U104#define TEGRA234_RESET_TACH0 95U105#define TEGRA234_RESET_TACH1 96U106#define TEGRA234_RESET_SPI5 97U107#define TEGRA234_RESET_TSEC 98U108#define TEGRA234_RESET_UARTI 99U109#define TEGRA234_RESET_UARTA 100U110#define TEGRA234_RESET_UARTB 101U111#define TEGRA234_RESET_UARTC 102U112#define TEGRA234_RESET_UARTD 103U113#define TEGRA234_RESET_UARTE 104U114#define TEGRA234_RESET_UARTF 105U115#define TEGRA234_RESET_UARTJ 106U116#define TEGRA234_RESET_UARTH 107U117#define TEGRA234_RESET_UFSHC 108U118#define TEGRA234_RESET_UFSHC_AXI_M 109U119#define TEGRA234_RESET_UFSHC_LP_SEQ 110U120#define TEGRA234_RESET_RSVD_111 111U121#define TEGRA234_RESET_VI 112U122#define TEGRA234_RESET_VIC 113U123#define TEGRA234_RESET_XUSB_PADCTL 114U124#define TEGRA234_RESET_VI2 115U125#define TEGRA234_RESET_PEX0_CORE_0 116U126#define TEGRA234_RESET_PEX0_CORE_1 117U127#define TEGRA234_RESET_PEX0_CORE_2 118U128#define TEGRA234_RESET_PEX0_CORE_3 119U129#define TEGRA234_RESET_PEX0_CORE_4 120U130#define TEGRA234_RESET_PEX0_CORE_0_APB 121U131#define TEGRA234_RESET_PEX0_CORE_1_APB 122U132#define TEGRA234_RESET_PEX0_CORE_2_APB 123U133#define TEGRA234_RESET_PEX0_CORE_3_APB 124U134#define TEGRA234_RESET_PEX0_CORE_4_APB 125U135#define TEGRA234_RESET_PEX0_COMMON_APB 126U136#define TEGRA234_RESET_RSVD_127 127U137#define TEGRA234_RESET_NVHS_UPHY_PLL1 128U138#define TEGRA234_RESET_PEX1_CORE_5 129U139#define TEGRA234_RESET_PEX1_CORE_5_APB 130U140#define TEGRA234_RESET_GBE_UPHY 131U141#define TEGRA234_RESET_GBE_UPHY_PM 132U142#define TEGRA234_RESET_NVHS_UPHY 133U143#define TEGRA234_RESET_NVHS_UPHY_PLL0 134U144#define TEGRA234_RESET_NVHS_UPHY_L0 135U145#define TEGRA234_RESET_NVHS_UPHY_L1 136U146#define TEGRA234_RESET_NVHS_UPHY_L2 137U147#define TEGRA234_RESET_NVHS_UPHY_L3 138U148#define TEGRA234_RESET_NVHS_UPHY_L4 139U149#define TEGRA234_RESET_NVHS_UPHY_L5 140U150#define TEGRA234_RESET_NVHS_UPHY_L6 141U151#define TEGRA234_RESET_NVHS_UPHY_L7 142U152#define TEGRA234_RESET_NVHS_UPHY_PM 143U153#define TEGRA234_RESET_DMIC5 144U154#define TEGRA234_RESET_APE 145U155#define TEGRA234_RESET_PEX_USB_UPHY 146U156#define TEGRA234_RESET_PEX_USB_UPHY_L0 147U157#define TEGRA234_RESET_PEX_USB_UPHY_L1 148U158#define TEGRA234_RESET_PEX_USB_UPHY_L2 149U159#define TEGRA234_RESET_PEX_USB_UPHY_L3 150U160#define TEGRA234_RESET_PEX_USB_UPHY_L4 151U161#define TEGRA234_RESET_PEX_USB_UPHY_L5 152U162#define TEGRA234_RESET_PEX_USB_UPHY_L6 153U163#define TEGRA234_RESET_PEX_USB_UPHY_L7 154U164#define TEGRA234_RESET_PEX_USB_UPHY_PLL0 159U165#define TEGRA234_RESET_PEX_USB_UPHY_PLL1 160U166#define TEGRA234_RESET_PEX_USB_UPHY_PLL2 161U167#define TEGRA234_RESET_PEX_USB_UPHY_PLL3 162U168#define TEGRA234_RESET_GBE_UPHY_L0 163U169#define TEGRA234_RESET_GBE_UPHY_L1 164U170#define TEGRA234_RESET_GBE_UPHY_L2 165U171#define TEGRA234_RESET_GBE_UPHY_L3 166U172#define TEGRA234_RESET_GBE_UPHY_L4 167U173#define TEGRA234_RESET_GBE_UPHY_L5 168U174#define TEGRA234_RESET_GBE_UPHY_L6 169U175#define TEGRA234_RESET_GBE_UPHY_L7 170U176#define TEGRA234_RESET_GBE_UPHY_PLL0 171U177#define TEGRA234_RESET_GBE_UPHY_PLL1 172U178#define TEGRA234_RESET_GBE_UPHY_PLL2 173U179 180/** @} */181 182#endif183