106 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (C) 2020 Xilinx, Inc.4 */5 6#ifndef _DT_BINDINGS_VERSAL_RESETS_H7#define _DT_BINDINGS_VERSAL_RESETS_H8 9#define VERSAL_RST_PMC_POR (0xc30c001U)10#define VERSAL_RST_PMC (0xc410002U)11#define VERSAL_RST_PS_POR (0xc30c003U)12#define VERSAL_RST_PL_POR (0xc30c004U)13#define VERSAL_RST_NOC_POR (0xc30c005U)14#define VERSAL_RST_FPD_POR (0xc30c006U)15#define VERSAL_RST_ACPU_0_POR (0xc30c007U)16#define VERSAL_RST_ACPU_1_POR (0xc30c008U)17#define VERSAL_RST_OCM2_POR (0xc30c009U)18#define VERSAL_RST_PS_SRST (0xc41000aU)19#define VERSAL_RST_PL_SRST (0xc41000bU)20#define VERSAL_RST_NOC (0xc41000cU)21#define VERSAL_RST_NPI (0xc41000dU)22#define VERSAL_RST_SYS_RST_1 (0xc41000eU)23#define VERSAL_RST_SYS_RST_2 (0xc41000fU)24#define VERSAL_RST_SYS_RST_3 (0xc410010U)25#define VERSAL_RST_FPD (0xc410011U)26#define VERSAL_RST_PL0 (0xc410012U)27#define VERSAL_RST_PL1 (0xc410013U)28#define VERSAL_RST_PL2 (0xc410014U)29#define VERSAL_RST_PL3 (0xc410015U)30#define VERSAL_RST_APU (0xc410016U)31#define VERSAL_RST_ACPU_0 (0xc410017U)32#define VERSAL_RST_ACPU_1 (0xc410018U)33#define VERSAL_RST_ACPU_L2 (0xc410019U)34#define VERSAL_RST_ACPU_GIC (0xc41001aU)35#define VERSAL_RST_RPU_ISLAND (0xc41001bU)36#define VERSAL_RST_RPU_AMBA (0xc41001cU)37#define VERSAL_RST_R5_0 (0xc41001dU)38#define VERSAL_RST_R5_1 (0xc41001eU)39#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU)40#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U)41#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U)42#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U)43#define VERSAL_RST_SYSMON_LPD (0xc410023U)44#define VERSAL_RST_PDMA_RST1 (0xc410024U)45#define VERSAL_RST_PDMA_RST0 (0xc410025U)46#define VERSAL_RST_ADMA (0xc410026U)47#define VERSAL_RST_TIMESTAMP (0xc410027U)48#define VERSAL_RST_OCM (0xc410028U)49#define VERSAL_RST_OCM2_RST (0xc410029U)50#define VERSAL_RST_IPI (0xc41002aU)51#define VERSAL_RST_SBI (0xc41002bU)52#define VERSAL_RST_LPD (0xc41002cU)53#define VERSAL_RST_QSPI (0xc10402dU)54#define VERSAL_RST_OSPI (0xc10402eU)55#define VERSAL_RST_SDIO_0 (0xc10402fU)56#define VERSAL_RST_SDIO_1 (0xc104030U)57#define VERSAL_RST_I2C_PMC (0xc104031U)58#define VERSAL_RST_GPIO_PMC (0xc104032U)59#define VERSAL_RST_GEM_0 (0xc104033U)60#define VERSAL_RST_GEM_1 (0xc104034U)61#define VERSAL_RST_SPARE (0xc104035U)62#define VERSAL_RST_USB_0 (0xc104036U)63#define VERSAL_RST_UART_0 (0xc104037U)64#define VERSAL_RST_UART_1 (0xc104038U)65#define VERSAL_RST_SPI_0 (0xc104039U)66#define VERSAL_RST_SPI_1 (0xc10403aU)67#define VERSAL_RST_CAN_FD_0 (0xc10403bU)68#define VERSAL_RST_CAN_FD_1 (0xc10403cU)69#define VERSAL_RST_I2C_0 (0xc10403dU)70#define VERSAL_RST_I2C_1 (0xc10403eU)71#define VERSAL_RST_GPIO_LPD (0xc10403fU)72#define VERSAL_RST_TTC_0 (0xc104040U)73#define VERSAL_RST_TTC_1 (0xc104041U)74#define VERSAL_RST_TTC_2 (0xc104042U)75#define VERSAL_RST_TTC_3 (0xc104043U)76#define VERSAL_RST_SWDT_FPD (0xc104044U)77#define VERSAL_RST_SWDT_LPD (0xc104045U)78#define VERSAL_RST_USB (0xc104046U)79#define VERSAL_RST_DPC (0xc208047U)80#define VERSAL_RST_PMCDBG (0xc208048U)81#define VERSAL_RST_DBG_TRACE (0xc208049U)82#define VERSAL_RST_DBG_FPD (0xc20804aU)83#define VERSAL_RST_DBG_TSTMP (0xc20804bU)84#define VERSAL_RST_RPU0_DBG (0xc20804cU)85#define VERSAL_RST_RPU1_DBG (0xc20804dU)86#define VERSAL_RST_HSDP (0xc20804eU)87#define VERSAL_RST_DBG_LPD (0xc20804fU)88#define VERSAL_RST_CPM_POR (0xc30c050U)89#define VERSAL_RST_CPM (0xc410051U)90#define VERSAL_RST_CPMDBG (0xc208052U)91#define VERSAL_RST_PCIE_CFG (0xc410053U)92#define VERSAL_RST_PCIE_CORE0 (0xc410054U)93#define VERSAL_RST_PCIE_CORE1 (0xc410055U)94#define VERSAL_RST_PCIE_DMA (0xc410056U)95#define VERSAL_RST_CMN (0xc410057U)96#define VERSAL_RST_L2_0 (0xc410058U)97#define VERSAL_RST_L2_1 (0xc410059U)98#define VERSAL_RST_ADDR_REMAP (0xc41005aU)99#define VERSAL_RST_CPI0 (0xc41005bU)100#define VERSAL_RST_CPI1 (0xc41005cU)101#define VERSAL_RST_XRAM (0xc30c05dU)102#define VERSAL_RST_AIE_ARRAY (0xc10405eU)103#define VERSAL_RST_AIE_SHIM (0xc10405fU)104 105#endif106